Interface Design Principle of DS2450 Converter

In normal mode, the serial communication rate is 16.3kbps, while the rate in overspeed mode can reach 142kbps. The on-chip 16-bit cyclic redundancy check code generator can be used to detect the correctness of communication. DS2450 is a single-bus four-channel successive approximation A/D converter chip produced by DALLAS. Its input voltage range, conversion precision bit and alarm threshold voltage are all programmable; each channel can use its own memory to store parameters such as voltage range settings, conversion results and threshold voltage. DS2450 uses an 8-pin SOIC small package. It can be powered by a single 5V power supply or a parasitic power supply. The power consumption of the chip is only 2.5mW when it is working normally and 25μW when it is idle. Multiple DS2450 or other single-bus chips with MicroLAN interface can be connected in parallel. The CPU only needs one port line to communicate with many single-bus chips, and it occupies fewer ports of the microprocessor, so a large number of pins and logic circuits can be saved.

1 DS2450 pinout and internal structure DS2450 PDF download

1.1 Pin Function

DS2450 uses 8-pin SOIC package, and its pin functions are described as follows:

Pin 1 (VDD): working power supply input terminal;
Pin 2 (N.C): floating pin;
Pin 3 (DATA): serial data input/output terminal;
Pin 4 (GND): ground terminal;
Pin 5 (AIN-A): A-channel analog voltage input terminal;
Pin 6 (AIN-B): B-channel analog voltage input terminal;
Pin 7 (AIN-C): C-channel analog voltage input terminal;
Pin 8 (AIN-D): D-channel analog voltage input terminal.
1.2 Internal structure

The internal structure of DS2450 is shown in Figure 1. The 64-bit serial number in the photolithography ROM is photolithography-prepared before leaving the factory, and it can be regarded as the address serial code of the DS2450. The arrangement of the 64-bit photolithography ROM is: the first 8 bits (20H) are the product type number, the next 48 bits are the serial number of the DS2450 itself, and the last 8 bits are the cyclic redundancy check code of the previous 56 bits (CRC=X8+X5+X4+1); the role of the photolithography ROM is to make the address of each single bus device different, so that multiple single bus chips can be connected on one bus.

For a 1-wire port, other functions cannot be realized before the ROM function is established. The bus controller must first provide a ROM function control command (8 bits) to the DS2450 through the DATA pin. Its 7 function control commands are:

(1) Read ROM, command word [33H];

(2) Matching ROM [55H];

(3) Search ROM [F0H];

(4) Skip ROM [CCH];

(5) Conditional search ROM [ECH];

(6) Overspeed skip ROM [3CH];

(7) Overspeed matching ROM [69H].

The execution of the Overspeed Skip ROM or Overspeed Match ROM commands can make the serial communication rate as high as 142kbps. If multiple devices are connected on one line, these commands can operate on the 64-bit ROM part of each device and select a specific device. Then the next step of A/D conversion control commands and read/write memory commands are executed on the selected DS2450. All commands or data read/writes start from the lowest bit.

1.3 Memory

The DS2450 has 24 connected 8-bit memories inside, which can be divided into 3 pages, 8 bytes per page. Page 0 is the A/D conversion result memory, each channel occupies 2 bytes, a total of 16 bits. When the chip is powered on and reset, this page is cleared to 0; Page 1 is the A/D conversion control and status memory; Page 2 is the input high/low limit alarm value memory for each channel.

2 Conversion and read/write control

2.1 Conversion Control

The conversion control of DS2450 first sends the conversion command word [3CH] serially through its DATA terminal, then sends the channel selection word and preset control word, and finally starts the A/D converter for conversion. The meaning of each bit of the channel selection word and preset control word of DS2450 is listed in Table 1.

In the channel selection word, the corresponding bit is 1, indicating that the channel participates in the conversion. When multiple channels are selected at the same time, the conversion order is A→B→C→D, and the unselected channels will be skipped. The A/D conversion time can be approximated as:

Conversion time = number of channels × number of conversion accuracy bits × 80μs + 160μs.

When all channels have been converted, the system will issue a read memory command to obtain the conversion results and corresponding status.

The preset control word can be used to preset the conversion result memory of the corresponding channel. When SET, CLR = 00, it is not preset, that is, the last conversion value is kept; when SET, CLR = 01, it is preset to all 0 before conversion; when SET, CLR = 10, it is preset to all 1; and SET, CLR = 11 is an invalid combination.

2.2 Memory read/write control

The read memory command can be used to read conversion results, working status, threshold setting values, etc. The bus manager first sends out the read memory command word [AAH], and then sends out two bytes of 16-bit "starting data" memory address, and after reading a byte of data on the bus, the address automatically increases by 1, and then reads the next data; when a page is read, the next two bytes read are the 16-bit cyclic redundancy check code automatically generated internally, which is generated by the command word, address and memory data sent previously and according to the following expression:

CRC16=X16+X15+X2+1

The write memory command is mainly for the 1st and 2nd page memories, and its purpose is to write the working mode control word of each channel and the high and low threshold setting values ​​of the corresponding channel. The bus manager first sends the write memory command word [55H], then sends the two-byte 16-bit memory start address, and then sends the data to be written one by one, and its address is also automatically increased by 1. If a read operation is performed just after writing a data, the data read out should be exactly the data written last time. This feature can be used to compare the written and read data to determine the correctness of the transmission.

If a transmission error is found during the software check, the DS2450 chip must be initialized and the read/write operation must be repeated.

2.3 DS2450 working sequence

The first-line working protocol flow of DS2450 is: initialization → ROM function command → memory read/write/convert control function command → data transmission. Its working sequence includes initialization sequence, write sequence and read sequence. Figure 2 shows the working sequence in normal working mode.

3 Typical interface design between DS2450 and MCU

Figure 3 is a typical connection circuit between MCS-51 series microcontroller and DS2450. The DATA terminal of DS2450 is connected to P1.0 of AT89C51. The circuit adopts external power supply mode, and the VCC terminal of DS2450 is powered by 5V power supply. In this example, only D channel is converted into A/D, AIN-D is connected to analog signal input; AIN-A and AIN-B are connected to pull-up resistors to power supply, and their output can be used as high and low limit alarm signals of D channel.

If the crystal frequency used in the microcontroller system is 12MHz, then three subroutines can be written according to the initialization timing, write timing, and read timing of the DS2450: INIT is the initialization subroutine, which can be used to send a reset pulse and receive a presence pulse; WRITE is the write (command or data byte) subroutine; READ is the read data subroutine. All commands or data bytes to be read or written are placed in the A register.

To complete A/D conversion by controlling DS2450 through the host, the following steps are generally required: initialization, sending ROM function commands and corresponding 64-bit photolithography ROM data, selecting a specific chip, writing working mode control words and high/low limit thresholds, sending conversion control commands, reading conversion values ​​and status, etc.

If the D channel is set to 5.1V input range, the conversion accuracy is 12 bits, the high alarm threshold is 3.0V (96H), the low alarm threshold is 2.0V (64H), and channel A and channel B are used as alarm outputs, and finally the conversion results are placed at 30H and 31H, then the specific program list of its subroutine CTLAD is as follows:

CTLAD: LCALLINIT; sends a reset pulse and receives a presence pulse

If there are multiple DS2450s and other single-bus interface chips connected on one line, the writing of the subroutine CTLAD that uses parasitic power supply and overspeed mode and requires verification during communication may be more complicated.