Research on the Setting and Application of 80C51 Reset Flag

introduction

Setting the reset flag bit is convenient for distinguishing resets caused by different reasons. As a new technology, it is adopted by more and more new MCUs. For example, Philips' P87LPC700 and P89LPC900 series, Freescale's (formerly Motorola Semiconductor Division) MC68HC05 series and MC68HC08 series, Sunplus' SPMC65 series, Microchip's PIC series, etc., all have internal status registers designed specifically for recording various reset flags.

The MC68HC08 series has a reset status register that is responsible for recording 6 reset flags: power-on reset, pin reset, watchdog reset, illegal instruction reset, illegal address reset, and undervoltage reset. The SPMC65 series has a system control register that is responsible for recording 5 reset flags: power-on reset, external reset, watchdog reset, illegal address reset, and undervoltage reset. The 51-compatible P89LPC900 series has a reset source register that is responsible for recording 6 reset flags: undervoltage reset, power-on reset, external reset, watchdog reset, software reset, and UART received interval character reset (mainly as one of the ways to enter the ISP monitoring program). Even the AT89S51/52 and P89C52X2, which are commonly used by beginners, have added a power-on flag POF in their power control register PCON.

1 How to set the reset flag

The traditional 80C51 microcontroller does not have a reset flag recording function, which is a pity. Can this shortcoming be made up by certain technical means? Here is an inspiration and guidance for the majority of 80C51 microcontroller users.

The realization of the record of the reset flag bit definitely requires certain hardware circuit support, and there is no fixed pattern for the design of such a circuit. The author uses a MAX813L to design a support circuit, as shown in Figure 1, for readers' reference only.

Figure 1 80C51 reset flag support circuit

In Figure 1, a 4-input "NAND" gate G1 and a push button switch SW1 are used, and the 5 I/O pins P1.0~P1.4 of 80C51 and an external interrupt source INT0 are occupied. In addition, INT0 is set as the only high-level interrupt source through the initialization software in advance, the falling edge trigger mode is valid, and the general interrupt enable bit EA is opened. Usually, G1 maintains a high level because all input terminals are maintained at a high level, so its output terminal also maintains a high level. A massive capacitor C1 is used in the circuit as an energy storage device, playing the role of a backup battery. Due to the presence of diode D1, during the power failure of the main power supply, C1 only powers the microcontroller, and the 80C51 should be allowed to enter the shutdown state (PD mode) with the lowest energy consumption.

Based on the circuit in Figure 1 and with the necessary user software, 6 flag bits can be saved to record 7 reset flags after 7 different reset sources cause reset, which are explained below. A byte can be allocated in advance in the bit addressing range of the RAM, such as the 20H unit, to record the 6 reset flag bits, as listed in Table 1.

Table 1 User-defined system reset flag register (SRFR)

Assume that the register is named SRFR (System Reset Flag Register), the byte address is 20H, and only 6 bits out of 8 bits are used. Bit5~bit0 record manual reset, undervoltage reset, watchdog reset, illegal address reset, hardware and software reset, and software reset respectively.

① MRST: Manual reset. When the reset button SW1 is pressed, the INT0 interrupt is triggered; the state of the input pin P1.4 is detected in the interrupt service program. If P1.4=0, MRST is set to record that a manual reset operation has occurred. Then an active reset operation is performed by outputting a low level from the output pin P1.0 to the input pin MR of the MAX813L. After a delay from the MAX813L, a high level reset signal is sent from the output terminal RESET to the 80C51, causing it to perform a hardware reset operation.

② LVR: Undervoltage reset. When the upstream power supply voltage starts to drop and drops below the PFI detection threshold of MAX813L, the output terminal PFO sends a low level, triggering the INT0 interrupt; the state of the input pin P1.3 is detected in the interrupt service program. If P1.3=0, LVR is set to record that an undervoltage reset operation has occurred; then an active reset operation (the method is the same as above) is performed, or the microcontroller is shut down to save energy and maintain data, and wait for the main power supply to be restored.

③ WDR: Watchdog reset. When a watchdog overflow occurs, the output terminal WDO of MAX813L sends a low level, triggering the INT0 interrupt; the state of the input pin P1.2 is detected in the interrupt service program. If P1.2=0, WDR is set to record that a watchdog reset operation has occurred; then an active reset operation is performed (the method is the same as above). The watchdog feeding operation uses an I/O pin P1.1.

④ IAR: Illegal address reset. When an illegal address occurs, the output terminal PSEN of 80C51 sends a low-level instantaneous pulse, which will also trigger an INT0 interrupt; the status of the input pins P1.4~P1.2 is detected in the interrupt service program. If P1.4~P1.2=111, IAR is set, indicating that an illegal address reset operation has occurred; then an active reset operation is performed (the method is the same as above).

⑤ SHR: Software and hardware reset. When a software trap capture event or a software watchdog overflow event occurs, SHR can be directly set to indicate that a software and hardware reset operation has occurred; then an active reset operation is performed (the method is the same as above). If T0 is used as a software WDT, the INT0 and T0 interrupt sources should be set as high-level interrupts at the same time.

⑥ SWR: Software reset. When a software trap capture event or a software watchdog overflow event occurs, SWR can also be directly set to indicate that a software reset operation has occurred; then the software reset program SWRST can be called. The software reset program is written as follows:

SWRST:; Define the actual entry address of the software reset program
CLREA; First turn off the interrupt source enable bit
SETBF0; Set a software reset flag
MOVP0, #0FFH; Set the general port P0 to high-impedance input state
MOVP1, #0FFH; Set the general port P1 to high-impedance input state
MOVP2, #0FFH; Set the general port P2 to high-impedance input state
MOVP3, #0FFH; Set the general port P3 to high-impedance input state
MOVPSW, #00H; Set the program status word register to the original value
; (Other SFRs can also be initialized as needed)
MOVDPTR, #SWR0; Prepare the pop-up address for RETI without changing
the execution order
PUSHDPL; Push the low byte on the stack, first
PUSHDPH; Push the high byte on the stack, then
RETI; Interrupt return instruction, clear the high-level interrupt activation
trigger
SWR0:
CLRA; Prepare the reset address
PUSHACC; Push the low byte 00H
PUSHACC; Push the high byte 00H
RETI; Clear the low-level interrupt activation trigger and jump to
; 0000H

⑦ POR: Power-on reset. Although there is no POR flag directly set in the user-defined system reset flag register (SRFR), if the above 6 flags are detected to be 0 at the same time, it indicates that a power-on reset was performed before. The reason is that after experimental verification (the microcontroller model used in the experiment is SST89C58), at each initial power-on, the contents of the 80C51 internal RAM range (00H~7FH), including the 20H unit of RAM, are all automatically cleared; at each RST pin reset (or software reset), its contents remain unchanged. And each SFR is restored to its original value (also known as reset value) whether it is a power-on reset or a RST pin reset, as listed in Table 2.

Table 2 Reset of on-chip rewritable memory space

For newer microcontrollers (such as AT89S51/52, AT89S8252, AT89C53, AT89C55WD, AT89C51RC and P89C51X2/52X2/54X2/58X2, etc.) that only add one reset flag (represented as POF in the technical manual), the POR flag set here is no longer needed.

For single-chip microcomputer application systems that are not equipped with a backup power supply, you can also consider using E2PROM to transfer the reset flag at the moment before power failure, so that it will not disappear completely after power failure. In this case, you can choose a circuit solution with an external E2PROM data storage device (such as 8-pin serial 24C01, 93C46 or 25C040, etc.), or you can choose a single-chip microcomputer model with an internal E2PROM data storage device, such as AT89S8252, etc. In this way, the E2PROM programming operation can be completed by using a small amount of residual energy on the power filter capacitor C2 at the moment before power failure.

2 Application method of reset flag

The general method of writing the initialization program section is very simple, but it is only suitable for those single-chip microcomputer projects with low requirements and simple functions. Such projects (such as single-chip microcomputer applications such as some small household appliances) almost do not have strong "process" or "uninterrupted" characteristics, and the reset operation that may occur at any time and the user program that is re-run from the beginning will not have much impact or destructive consequences.

For single-chip microcomputer projects that have strong requirements for "process" or "continuity", once an accidental reset operation occurs and the user program is re-run from the beginning, it will bring great negative effects or destructive consequences. For example, a bread machine controlled by a single-chip microcomputer will go through processes such as mixing and heating during the process of making bread; if an accidental reset occurs and the program is re-executed from the beginning, it will become waste or burn. If a computer-controlled surgical robot is accidentally reset and reworked during an operation, it will bring unimaginable serious consequences. If a computer-controlled missile is accidentally reset and the program is re-executed from the beginning during the flight after it is aimed at the target and launched, it will produce unpredictable results.

In summary, if it is inevitable that the microcontroller will be reset due to unexpected interference during operation, then where to start running the program or under what background after the reset can be arranged manually. Therefore, the application method of the reset flag is essentially the writing method of the reset handler. The processing flow of the reset handler is shown in Figure 2.

Figure 2 Reset processing flow

Similar to the idea of ​​writing a UART serial communication interrupt service program, after entering the interrupt program, the interrupt flag bit must be checked first to see if it is a receive interrupt (RI=1) or a send interrupt (SI=1), and then enter different program branches for targeted services. As can be seen from Figure 2, when executing the user program from the reset vector 0000H, the reset flag register should be checked first to determine whether it is a reset caused by the initial power-on or other reset sources or the program counter PC is cleared.

① If the power is initially turned on, the original state is initialized. This is the simplest case.

② If the program is out of order and caused by software reset, hardware or software reset, illegal address reset, or manual forced reset, the data should be restored or parameters should be corrected as much as possible according to the specific situation, so as to minimize or minimize the impact on the normal operation of the program (the specific algorithms for restoring and correcting data will not be discussed in depth here).

③ If it is an undervoltage reset, try to restart the program from the interrupted program breakpoint. The specific implementation method and steps can be: Before reset - after the microcontroller responds to the PFO interrupt request and enters its service program, it saves the current value of the stack pointer SP to the specified RAM unit and pushes the microcontroller into the shutdown state; After reset - after the power is restored, MAX813L is powered and sends a high-level signal from the RESET terminal to wake up the microcontroller in the shutdown state. If the awakened microcontroller detects that it is an undervoltage reset, it first restores the previous SP value, and then uses a RET (or RETI) instruction to pop out the program breakpoint before the shutdown to the PC, so that the previous task can continue to execute.

References

[1] Li Xuehai. PIC Microcontroller Practical Tutorial - Basics/Extended Edition. Beijing: Beijing University of Aeronautics and Astronautics Press, 2002.
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