Design of single CPU emulator for microcontroller

Abstract : Based on an in-depth analysis of the storage space structure of the 8051 microcontroller, this article proposes a design scheme for a single CPU emulator based on the microcontroller. This solution is practical, cheap, and highly practical in engineering, and can be used to design new teaching equipment.

Introduction

Microcontrollers have broad market prospects due to their cheapness, small size, strong plasticity and high stability. When developing products with microcontrollers, although many manufacturers have designed programmable ISP microcontrollers, from the perspective of safety and convenience, microcontroller emulators are still an indispensable tool for developers. The microcontroller emulator can be used to replace the microcontroller for software and hardware debugging during the product development stage, thereby quickly discovering and correcting errors in the program, and greatly shortening the microcontroller development cycle. However, in practice, emulators are too expensive. Therefore, designing and producing a cheap and practical emulator has a wide market.

There are generally three implementation methods for traditional microcontroller emulator hardware systems. 1. Use a dedicated simulation microcontroller. 2. Use two sets of microcontrollers. One microcontroller is used for simulation and completes functions such as communication and interrupts. The other microcontroller is used for the target microcontroller, so that its resources will not be occupied. 3. Use the target microcontroller as the emulator. The microcontroller, the emulator, is also used as the target microcontroller. It is essentially a ROM monitor. The third method will occupy part of the resources of the microcontroller, but it has a simple structure. For specific developers, it is highly practical, cost-effective, and easy to make by themselves. The simulator developed and designed in this article is based on the third principle, cleverly realizing the exchange of data space and program space, and designing a practical and cheap simulator with strong engineering practice.

Principle and System Structure

When the simulator works, the program must be downloaded from the PC to the memory of the simulator. Here we first analyze the memory structure and addressing method of the 51 single chip in detail, then analyze the expansion of off-chip memory, and finally give the design principles and analyze the system structure.

Figure 1 Storage space distribution

51 Microcontroller Memory Structure Analysis

The memory of the 8051 microcontroller is physically divided into program memory space and data memory space. There are 4 storage spaces: on-chip program memory, off-chip program memory, on-chip data memory, and off-chip data memory space. This structure that separates program storage and data storage is called Harvard structure. But from the user's point of view, the 8051 memory address space can be divided into three categories: the 64KB program memory address space with unified on-chip and off-chip addresses 0000H~FFFFH (using a 16-bit address); the 64KB off-chip data memory address space, the address is also Addressing from 0000H~FFFFH (using 16-bit address); 256B on-chip data memory address space (using 8-bit address).

The above four storage space addresses overlap, as shown in Figure 1. The 8051 instruction system has designed different data transfer instructions to distinguish these four different logical spaces: MOVC is used by the CPU to access on-chip and off-chip ROM instructions, MOVX is used to access off-chip RAM instructions, and MOV is used to access on-chip RAM instructions.

Program memory is used to store programmed programs and table constants. The program is addressed through a 16-bit program counter, with an addressing capacity of 64KB. This allows instructions to jump arbitrarily within the 64KB address space, but does not allow the program to move from program memory space to data memory space.

In fact, when the pin EA is connected to high level, the program counter PC of the 8051 executes the program in the on-chip ROM. When the instruction address exceeds the on-chip ROM address, it automatically turns to the off-chip ROM to fetch the instruction. When pin EA is connected to low level (grounded), the 8051 on-chip ROM does not work. The CPU can only fetch instructions from the off-chip ROM, and the address can be addressed starting from 0000H. The 8051 executes at the same speed when fetching instructions from on-chip program memory and off-chip program memory.

Memory expansion 

Use the P0 port as the address/data multiplexing bus, and use the P2 port line as the high-order address line. You can expand the memory up to 64KB. The control signal lines include: using ALE as the strobe signal of the address latch to realize the latch of the lower 8-bit address; using the PSEN signal as the read strobe signal of the extended program memory; using the EA signal as the selection of internal and external program memory Signal; use EA and as read and write strobe signals for extended data memory and I/O ports. When executing the MOVX instruction, the RD and WR signals are automatically valid respectively. The reading and writing of the off-chip data memory RAM are controlled by the RD (P3.7) and WR (P3.6) signals of the 8051, while the output enable (OE) of the off-chip program memory is controlled by the read strobe PSEN signal. Although the off-chip data memory and the off-chip program memory coexist in the same address space, bus conflicts will not occur because the control signals and data transfer instructions used are different.

Figure 2 Simulator schematic diagram

Emulator Principle and Structure

Since almost all microcontrollers with 8051 as the core now have internal FLASH program memory. For example, the AT89C51 or AT89S51 used in this design all come with 4KB of FLASH program memory, and some microcontrollers have 20KB or more of program memory. Therefore, in the development of microcontrollers, special program memory chips are rarely used to expand external program memory, and it is usually unnecessary. Based on the above factors, the following analyzes the principles of the emulator implementation in this article.

When downloading the program, EA is connected to high level, the microcontroller executes the program in the internal ROM, and downloads the program data of the PC to the off-chip RAM62256; after the program data is downloaded, while keeping the RAM62256 from powering down, the The EA of the microcontroller is connected to a low level and the microcontroller is reset. In this way, the microcontroller can only read data from off-chip memory. Then use the "AND" of RD and PSEN to strobe the read enable chip select terminal OE of RAM62256, so that the microcontroller can read the program from RAM62256. In this way, the simulation function is realized. Because the execution speed of the microcontroller when fetching instructions from the on-chip program memory and the off-chip program memory is the same, the performance of the emulator under this design is not inferior to that of the traditional emulator.

The total system circuit principle is shown in Figure 2. The system consists of microcontroller AT89C51, address latch 74LS373, off-chip memory 62256, interface level conversion chip MAX232 and related control circuits.

Among them, AT89C51 is the core component of the emulator. The crystal oscillator circuit and reset circuit are the same as ordinary single-chip microcomputer systems. The difference is: EA is connected to a single-pole double-throw switch, and there is no expansion ROM on the surface. The connection method of RAM62256 is different from that of ordinary OE microcontroller system. In the system, RD is ANDed with PSEN, so that it can enable the RAM62256 to read and allow the chip select terminal OE to activate the RAM (Note: RAM does not operate during the whole process. Power outage) Conversion from the role of data space to the role of program space. When executing the MOVX instruction, RD and WR signals are generated and program information is written. When executing the program in the RAM, the OE end of the RAM62256 is gated by the PSEN signal and the RD signal to realize the reading of the program from the RAM62256.

For software design of

PC (host computer) software, you can refer to Windows driver development, serial port debugging assistant and other related books; you can also use the ready-made Windows integrated development environment of KEIL C51~VISION51 and software emulator DSCOPE51 to complete.

The main task of the lower computer software is to set up the serial port and receive the data sent from the upper computer's serial port, and store the data in the external "data" memory.

The main program of the microcontroller is as follows:
MOV SCON, #50H; Serial port mode 1
MOV TMOD, #20H; T1 mode 1
MOV TL1, #0FDH; Constant baud rate of 9600
MOV TH1, #0FDH SETB
TR1; Open interrupt
SETB ET1
SETB ES
SETB The EA
system uses the following instructions when "writing":
MOVX @DPTR,A
MOVX @Ri, A
In the interrupt service subroutine, in order to distinguish whether the received signal is a contact signal or a byte number, data or a checksum, it needs to be set up The different flag bits are as follows:
 FLAG0 BIT 00H; receiving contact signal flag bit
 FLAG1 BIT 01H; receiving byte number flag bit
 FLAG2 BIT 02H; receiving data flag bit
 FLAG3 BIT 03H; receiving file end flag bit    
program flow as shown in Figure 3. Among them, R7 is the number of bytes received. The received data must be stored in the off-chip RAM unit starting from 0000H. When the microcontroller is reset and the RAM is used as program memory, the PC starts from 0000H.

Figure 3 Microcontroller receiving interrupt service subroutine flow chart

Several points of discussion

(1) There is no need for a separate emulator power supply or crystal oscillator circuit in the system.
(2) The off-chip memory of the lower computer does not need to be erased when repeatedly writing data. It is always overwritten every time the program is re-downloaded. Newly downloaded programs all end with END. Even if the newly downloaded program is shorter than the original one, redundant code will not be executed.
(3) In practice, the circuit can be further improved. After the file is downloaded, a control signal is generated through the serial port backup signal line to control and reset, so that the entire process is controlled by the host computer.
(4) Due to internal structure limitations, the simulated product cannot expand the off-chip program memory, but since the off-chip data memory can be expanded to 64KB, only 32KB is used in this article, so certain peripherals can also be expanded.
(5) There are certain restrictions on the connection method of E(--)A(--) of the simulated product. It cannot be directly connected to the ground or the positive pole of the power supply. In practice, as long as a suitable current limiting resistor (such as 10K?) is added That's it. In fact, this solution can be applied to any microcontroller that can expand memory.

Conclusion

After analyzing the above design, it is not difficult to find that the technology of each functional module of the entire system is very mature: in terms of hardware, each sub-circuit has existing circuit applications, and the parameters of each component are easy to determine; in terms of software, only The serial communication program of the COM port and the interface program of the host computer. In the actual production process, the system has a small number of components and is cheap, easy to debug, has a high success rate and stable performance.