51 MCU RTL8019AS network card driver

The SNMP network management board uses the RTL8019AS 10M ISA network card chip to access the Ethernet. The advantages of choosing it are: NE2000 compatibility, good software portability; simple interface without conversion chips such as PCI-ISA bridge; cheap price 2.1$/chip (my purchase price is 22 RMB/chip); sufficient bandwidth (for 51); will not be discontinued for a long time. 8019 has 3 configuration modes: jumper mode, plug-and-play P&P mode, and serial Flash configuration mode. In order to save costs, I removed 9346 and used X5045 as a flash drive to store MAC addresses and other configurable information. The P&P mode is used in PCs and is not used here. Only the jumper configuration mode is available. Its circuit design refers to the DEMO board drawings provided by REALTEK. It can be completed in one day, and the hardware design is relatively simple.

The software corresponding to this part of the hardware is the network card driver. The so-called driver refers to a group of subroutines that shield the underlying hardware processing details and provide hardware-independent interfaces to the upper-level software. The driver can be written as a subroutine and embedded in the application (such as I/O port operations and ISR under DOS), or it can be placed in a dynamic link library and dynamically loaded when used to save memory. In WIN98, in order to make the three modes of application programs of V86, WIN16, and WIN32 coexist, the concept of virtual machine was proposed. With the cooperation of the CPU, the system works in protection mode, the OS takes over I/O, interrupts, and memory access, and the application cannot directly access the hardware. This improves the system reliability and compatibility, but also brings about the problem of complex software programming. Any network card driver must be written in VXD or WDM mode. For the hardware side, it is necessary to handle virtual machine operations, bus protocols (such as ISA, PCI), plug-and-play, and power management; the upper-level software side must implement the NDIS specification. Therefore, it is quite complicated to implement a network card driver under WIN98.

The driver I am talking about here refers specifically to a set of hardware chip driver subroutines in real mode. From the programmer's perspective, the 8019 workflow is very simple. The driver writes the data packet to be sent into the chip in the specified format and starts the send command. The 8019 will automatically convert the data packet into a physical frame format for transmission on the physical channel. Conversely, after receiving the physical signal, the 8019 restores it to data and stores it in the chip RAM in the specified format for the host program to use. In short, the 8019 completes the mutual conversion between data packets and electrical signals: data packets <===> electrical signals. The Ethernet protocol is automatically completed by the chip hardware and is transparent to the programmer. The driver has three functions: chip initialization, packet reception, and packet transmission.

There is more than one Ethernet protocol, and I use 802.3. Its frame structure is shown in Figure 1. The sending and receiving operations on the physical channel all use this frame format. Among them, the preamble sequence, frame start bit, and CRC check are automatically added/deleted by the hardware and have nothing to do with the upper-layer software. It is worth noting that the format of the received data packet is not a true subset of the 802.3 frame, but as shown in Figure 2. Obviously, 8019 automatically adds three data members (4 bytes in total) of "receiving status, next page pointer, Ethernet frame length (in bytes)". The introduction of these data members facilitates the design of the driver and reflects the design idea of ​​​​software and hardware working together. Of course, the format of the sent data packet is a true subset of the 802.3 frame, as shown in Figure 3.

With the format of the send and receive packets, how to send and receive data packets? As shown in Figure 4, first store the data packet to be sent into the chip RAM, give the first address of the send buffer and the length of the data packet (write TPSR, TBCR0,1), and start the send command (CR=0x3E) to realize the 8019 sending function. 8019 will automatically complete the transmission according to the Ethernet protocol and write the result into the status register. As shown in Figure 5, the receive buffer constitutes a circular FIFO queue. The two registers PSTART and PSTOP define the start and end pages of the circular queue. CURR is the write pointer, which is controlled by the chip, and BNRY is the read pointer, which is controlled by the host program. According to CURR==BNRY+1?, it can be judged whether a new data packet is received. The newly received data packet is stored in the RAM with the address indicated by CURR as the first address according to the format of Figure 2. When CURR==BNRY, the chip stops receiving data packets. If you have done FPGA design and used VHDL, you can imagine the working principle of hardware chips. Here, two 8-bit registers and a 2-input comparator are designed. When a data packet is received, the receiving state machine determines the next state based on the current state and the comparator result. If CURR=BNRY, it enters the stop receiving state; otherwise, CURR increases by 1. The 8019 data manual does not give the implementation method of the hardware state machine, and the description is also very brief. It is often necessary to infer the working process through experiments. For example, the ISR register is not only related to interrupts. When the receiving buffer overflows, if the ISR is not cleared (write FFH), the chip will stop receiving. Overflow often occurs when the traffic is large. At this time, if the ISR is not cleared, the network card chip will crash.

Now that we understand the principle of sending and receiving data packets, how are data packets written into and read from the chip RAM by the host? As shown in Figure 6, the host sets the remote DMA start address (RSAR0,1) and the number of remote DMA data bytes (RBCR0,1), and sets read/write in CR, and then the data in the chip RAM can be read from the remote DMA port register/written into the chip RAM.

What is local/remote DMA? As shown in Figure 7, "remote" refers to the CPU interface side; "local" refers to the hardware transceiver circuit side of 8019. There is no deeper meaning, it has nothing to do with distance, it is just to distinguish the two interface ends of the host and chip hardware. The DMA here is a little different from the DMA we usually talk about. The local DMA operation of RTL8019AS is completed by the controller itself, while its remote DMA is not without the participation of the host processor, and the data can be automatically moved to the memory of the main processor. Remote DMA means that the host CPU can read and write the chip RAM by giving the starting address and length, and the RAM address is automatically increased by 1 each time the operation is performed. Ordinary RAM operations have to send the address first and then process the data each time, which is slower.

Some high-end communication controllers have built-in MAC controllers, and their working principle is similar to that of 8019. For example, the CPM inside Motorola 68360/MPC860T has an Ethernet processor. By setting the BD table, the software and hardware can work together, and its buffer is larger and can be flexibly configured. The design of these communication controllers reflects the trend of software and hardware working together: software hardening (VHDL) and hardware softening (DSP). I hope everyone will pay attention to it!

As shown in Figure 7, the 8019 Ethernet controller is based on memory (16K dual-port RAM), and the local and remote controllers operate concurrently. This architecture meets the needs of data bandwidth. The 8019 has control, status, and data registers, through which the 51 microcontroller can communicate with the 8019. Due to the limited resources of the 51, do not copy memory blocks when implementing the TCPIP protocol stack. It is recommended that (1) use global structure variables to save only one copy of the data packet in the memory, and other packets that have not been processed in time are saved in the 8019's 16K RAM; (2) use the query method without interruption; (3) the server in the client-server model works in serial mode, and the concurrent mode is not suitable for the 51 microcontroller.

The allocation of the chip's internal address space is shown in Figure 8, where 0x00-0x0B (working in 8-bit DMA mode) is used to store the MAC address of the node, and the parity address content is repeated. For example: MAC address 0000 1234 5678 is stored in 0x00-0x0B as 000000001212343456567878, and the single address and double address content are repeated. Generally, the even address content is used, which is mainly to adapt to both 8-bit and 16-bit DMA. The Prom content is read from the 93C46 when the network card is powered on and reset. If you don't use 93C46, don't use Prom. Then how to get the address of the network card after using 93C46? There are two methods, one is to read 93C46 directly, and the other is to read Prom. The MAC address of the network card is not determined by 93C46 or Prom, but by PAR0-PAR5 registers. Prom only saves the MAC address read from 9346 when powered on (if there is 93C46), nothing more.