Design of image processing system based on ISP technology and 89C55 single chip microcomputer

With the popularization of image processing technology, its application scope is getting wider and wider. In the fields of medicine, military, public security, etc., especially in recent years, it has been widely used in industrial automation and industrial detection. Most of the current image processing systems use computers plus video capture cards and cameras to form their hardware systems. This hardware structure is obviously not suitable for processing simple image processing systems that are not complex.

At present, the resources inside the EPLD chip are increasing, the speed is getting faster, and the software functions developed are more perfect, which gradually expands its application. It is generally believed that many electronic systems in the future will be characterized by the structure of CPU+RAM+EPLD. The image system will develop towards miniaturization. How to design a simple and low-cost image processing system is an urgent requirement to apply image processing technology to a wider range of fields.

The system introduced in this article is developed for such a demand.

1 Overall design plan

The whole system consists of a camera, an image input unit, an image storage unit, an image processing unit, an image display unit and a drive control unit. The block diagram of the image processing system is shown in Figure 1.

The image processing system uses Atmel's 89C55 as the central processing unit, and the system clock is 20MHz. The image acquisition part is provided by ISPLSI1032E to provide the address signal of the image RAM and the clock signal of the image acquisition dot matrix. Each frame of the image can be divided into 256×256 or 512×512 dot matrix according to the needs. In special cases, 256×128 or 512×256 half-screen mode can also be used. In the image output unit, the image and the display menu can be superimposed and output to form a visual menu.

In addition, in order to adapt to the application of industrial detection and industrial automation, a drive control circuit is also designed in the system, which can output switching and analog quantities. Basically, it can adapt to various control occasions.

2 Hardware Circuit Design

2.1 ISP Device Development

In addition to the ease of use and high performance of general PLD devices and the flexibility and high density of FPGA, the most important thing about ISP devices is its in-system programmable technology, that is, ISP can be soldered to the circuit board in a blank state. Any circuit board that has installed an ISP device can be upgraded with new programming code through a PC and a download cable, and all work can be done without powering off.

ISP (In SYSTEM PROGRAMMING) technology is the latest technology provided by LATTICE Semiconductor Company, which can configure or reorganize the logic and functions of its devices, circuit boards or the entire electronic system at any time in every link of the product design and manufacturing process, even after the product is sold to the end user.

In the system development process, the core part of image acquisition is how to store the result of A/D conversion of video signals into the memory, that is, how to generate the address signal of the memory according to the video signal. After estimating the number of required logic gates, we use ISPLSI1032 as the address generator and some other logic circuits.

2.2 Generation of image acquisition timing

Here, take 256×128 dot matrix as an example to illustrate the generation of image acquisition timing. A0~A7 represents the address of the dot matrix in each row, and A8~A14 represents the row address. The timing of its row valid signal and A0~A7 address is shown in Figure 2, and the timing of its field valid signal and A8~A14 address is shown in Figure 3. In this way, 256×128=32768 storage units are shared to store 1 image.

If it is necessary to capture an image, the CPU sends a START signal to the ISP, causing the ISP to disconnect the address line provided by the CPU to the image RAM, and the ISP generates the address A0~A14 of the image RAM instead. After the SIP generates the address of an image, it outputs an END signal to notify the CPU that the image capture is complete, and gives up the address line and data line of the RAM to the CPU for image processing.

There are 4 32K×8bit RAMs (62256) in the system, among which:

RAM1 is the image frame memory;
RAM2 is the graphic flag bit, used for image annotation;
RAM3 is the display memory of the menu interface;
RAM4 is the system memory, used to store the intermediate data and processing results of the processing.
Figure 4 is the schematic diagram of the image acquisition part.

In actual use, the CPU operates RAM1, RAM4 and RAM2, RAM3 in a time-sharing manner. During the scanning period, the CPU operates RAM1 and RAM4 to calculate and process the image; and during the retrace period, the menu and annotation are refreshed. The ISP operates RAM2 and RAM3 during the scanning period to synthesize the menu and annotation with the image.

ISPEXPERT is a complete ISP integrated development environment launched by LATTICE in the late 1990s. It has 500 macro components available for use, and supports VHDL, Verilog-HDL, ABELHDL and schematic compiler integrated development software; it can be used for logic design and optimization of ISP devices, logic mapping, automatic layout and routing, fuse map file generation and programming download. In addition, it can also perform functional simulation, timing simulation and static timing analysis on the designed digital system.

From the user's point of view, ISPEXPERT is more powerful and easier to operate than Workview office and Synario software.

This system uses the ISP1032E chip to omit the complex and large number of logic circuits, uses VHDL language programming, and is developed through the ISPEXPERT integrated development environment, which not only saves a lot of hardware debugging time, but also reduces mutual interference between lines. More importantly, it saves time for re-copying the board, greatly shortening the product development cycle.

Conclusion

The image processing system based on ISP and single-chip microcomputer has the characteristics of simple structure, high integration, small size and low price, and is particularly suitable for the development of embedded systems with image processing functions. This system has been used in practice and achieved good results.