s3c2440 bare metal - memory controller 2 - connection between different bit width peripherals and CPU address bus

Connecting devices with different bit widths

Let's first look at how the peripheral ROM is connected to the CPU address bus in the 2440 chip manual.

Connection between 8bit ROM and CPU address line

Connection between 8bit*2 rom and CPU address line

Connection between 8bit*4 rom and CPU address line

Connection between 16bit ROM and CPU address line

Connection between 16bit*2 rom and CPU address line

From the above figure, we know that two 8-bit peripherals can be cascaded to form a 16-bit peripheral. Similarly, four 8-bit peripherals can be cascaded to form a 32-bit peripheral.

From the above figure, we can also see a pattern:

When the peripheral bus width is 8 bits, peripheral A0 is connected to the CPU address bus ADDR[0].
A[1]->ADDR[1] ...A[15]->ADDR[15]

When the peripheral bus width is 16 bits, peripheral A0 is connected to the CPU address bus ADDR[1].
A[1]->ADDR[2] ...A[15]->ADDR[16]

When the peripheral bus width is 32 bits, peripheral A0 is connected to the CPU address bus ADDR[2].
A[1]->ADDR[3] ...A[15]->ADDR[17]

So why is it designed like this?

Let's look at an example: Assume the CPU executes:

MOV R0, #3
LDRB R1, [R0] @ Read a byte from memory address 3

As shown in the figure, there are 8bitROM, 16bitROM, 32bitROM

(1) For 8-bit ROM, 8 bits is the smallest unit of reading and writing at one time, that is, address 0 is the first 8 bits, and address 1 is the second 8 bits;

The CPU sends address 3, that is, A0 and A1 are both 1, and the 8-bit ROM's A0 and A1 also receive 1.

So we found the 8-bit data at address 3 on the ROM, which contains the data we need.

(2) For 16-bit ROM, 16 bits is the smallest unit of reading and writing at one time, that is, address 0 is the first 16 bits, which contains two 8-bit data;

The CPU sends address 3, that is, A0 and A1 are both 1, and the 16-bit ROM receives 1 and 0 respectively.

So we find the 16-bit data at address 1 on the ROM, which contains the data we need. Finally, the memory controller helps us select the required 8-bit data.

(3) For 32-bit ROM, 32 bits is the smallest unit of reading and writing at one time, that is, address 0 is the first 32 bits, which contains four 8-bit data;

The address 3 sent by the CPU, that is, A0 and A1 are both 0, and the A0 and A1 received by the 32-bit ROM are both 0.

So we find the 32-bit data at address 0 on the ROM, which contains the data we need. Finally, the memory controller helps us select the required 8-bit data.

Use a table to understand better:

in conclusion:

The peripheral address lines connected to the CPU address bus determine the address of the peripheral to be accessed, that is, which storage unit;

Then, after the memory controller obtains the data from the peripheral storage unit, it selects the corresponding data for the CPU based on the values ​​of the staggered pins [A1-A0] (the values ​​of the pins not connected to the CPU address bus).

Let's take another example: If you read a 32-bit data

MOV R0, #4

LDR R1, [R0] @Go to address 4, read 4 bytes of data

We know that the CPU issues a 32-bit address, so

For 16-bit Rom, the memory controller will send it twice, and the ROM will receive it twice accordingly;

For 8-bit Rom, the memory controller sends it 4 times, and the ROM receives it 4 times.

So how does the CPU know whether the bit width of its external ROM is 16bit, 8bit or something else?

Of course the memory controller knows and configures the bus width register. How to configure the bus width register

The execution process is as follows:

How to determine the access address of the chip?

1. Determine the base address based on the chip select signal
2. Determine the range based on the address lines connected to the chip

Here is another reminder, some people found that nor is not connected to CPU ADDR0, and sdram is not connected to CPU ADDR0 and ADDR1. Don't think that ADDR0 and ADDR1 are not used, because nor data width is 16 bits, ADDR0 is used for memory controller to split data, and sdram data width is 32 bits, ADDR0 and ADDR1 are also used for memory controller to split data. This has been analyzed above, and this is why the misaligned connection is required.