stc12c5a60s2 reset circuit description

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STC12C5A60S2 Among the many 51 series microcontrollers, the 1T enhanced series of the domestic STC company is more competitive, because it is not only fully compatible with 8051 instructions and pins, but also has a large-capacity program memory on the chip and is made of FLASH technology. For example, the STC12C5A60S2 microcontroller comes with up to 60K FLASHROM. Users of memory with this technology can instantly erase and rewrite using electricity. Moreover, STC series microcontrollers support serial port program programming. Obviously, this kind of microcontroller has very low requirements for development equipment and the development time is greatly shortened. The program written into the microcontroller can also be encrypted, which protects the fruits of your labor well.

stc12c5a60s2 internal structure diagram

The internal structure diagram of stc12c5a60s2 is as follows:


stc12c5a60s2 reset circuit description

stc12c5a60s2 reset circuit

Just connect a 10UF capacitor to the power supply + from the reset pin, and connect a 10K pull-down resistor at the same time. If you need to manually reset, you need to connect a button in parallel to both ends of the resistor. When powering on or after pressing the button, the resistor The charging of the capacitor produces a low-to-high reset on the reset pin.

basic skills:

1.8-bit data bus, 16-bit address bus CPU;

2. Have Boolean processing capabilities and bit processing capabilities;

3. Using Harvard structure, the program memory and data memory address spaces are independent, which facilitates program design;

4. 64KB program memory and 64KB data memory at the same address;

5.0-8KB on-chip program memory (8031 has none, 8051 has 4KB, 8052 has 8KB, 89C55 has 20KB);

6.128 bytes of on-chip data memory (8051 has 256 bytes);

7.32 bidirectional and bit-addressable I/O lines;

8. Two 16-bit timer/counters (8052 has 3);

9. A full-duplex serial I/O interface;

10. The interrupt structure of multiple interrupt sources has two interrupt priority levels;


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