S5PV210 clock

CLOCK DOMAINS clock domains

S5PV210 consists of three clock domains, namely, main system (MSYS), display system (DSYS), and peripheral system (PSYS)

Clock source
external soldering:

1.XRTCXTI: Real-time clock
2.XXTI: CPU clock
3.XUSBXTI: USB clock
4.XHDMIXTI: HDMI clock

Typical applications of CMU:

1.MSYS clock domain uses APLL (that is, ARMCLK, HCLK_MSYS, and PCLK_MSYS)
2.DSYS and PSYS clock domain (that is, HCLK_DSYS, HCLK_PSYS, PCLK_DSYS, and PCLK_PSYS) and other peripheral clocks (that is, audio IPs, SPI, and so on) use MPLL and EPLL
3.Video clocks uses VPLL

clock relationship

MSYS clock domain

− freq(ARMCLK) = freq(MOUT_MSYS) / n, where n = 1 ~ 8

− freq(HCLK_MSYS) = freq(ARMCLK) / n, where n = 1 ~ 8 //Fast

− freq(PCLK_MSYS) = freq(HCLK_MSYS) / n, where n = 1 ~ 8 //low speed

− freq(HCLK_IMEM) = freq(HCLK_MSYS) / 2 //Memory

• DSYS clock domain

− freq(HCLK_DSYS) = freq(MOUT_DSYS) / n, where n = 1 ~ 16

− freq(PCLK_DSYS) = freq(HCLK_DSYS) / n, where n = 1 ~ 8

• PSYS clock domain

− freq(HCLK_PSYS) = freq(MOUT_PSYS) / n, where n = 1 ~ 16

− freq(PCLK_PSYS) = freq(HCLK_PSYS) / n, where n = 1 ~ 8

− freq(SCLK_ONENAND) = freq(HCLK_PSYS) / n, where n = 1 ~ 8 //nand

PLL phase locked loop

1.APLL can drive MSYS domain and DSYS domain

2.MPLL can drive MSYS domain and DSYS domain

3.EPLL is mainly used to generate audio clock

4.VPLL is mainly used to generate video system operating clock

CLK_SRC0, R/W, Address = 0xE010_0200
PLL selection, by setting the corresponding bit

Frequency multiplication
takes APLL as an example

APLL_CON0, R/W, Address = 0xE010_0100

ERROR = MDIV * FIN / (PDIV * 2^(SDIV-1))

PDIV: 1 ≤ PDIV ≤ 63
MDIV: 16 ≤ MDIV ≤ 1023
SDIV: 0 ≤ SDIV ≤ 5

Common reference values

Multiply to 1G
input frequency, default 24M

ERROR = 125 * 24 / (3 * 2^(1-1)) = 1000