N76E003 Watchdog Timer WDCON

1. Reset function configuration

N76E003 provides a watchdog timer (WDT), which can be configured as a timeout reset timer to reset the entire device. Once the device enters an abnormal state or hangs due to external interference, the watchdog can reset and recover the system.

WDTEN[3:0] (CONFIG4[7:4]) initializes WDT to work in timeout reset timer or general timer mode.

2. General timer configuration

The WDT has an independent divider for dividing the 10K LIRC clock. The divider clock frequency can be selected to determine the timeout interval. When the timeout interval is reached, the system will be awakened from the idle or power-down mode, and an interrupt event will be generated if the WDT interrupt is enabled. If the WDT is initialized as a timeout reset timer, a system reset will be generated after a delay period without any software action.

Timeout reset timer

When the CONFIG bit WDTEN[3:0] (CONFIG4[7:4]) is not FH, the WDT will be initialized as a time-out reset timer. If WDTEN[3:0] is not 5H, the WDT is allowed to continue running after the system enters the idle or power-down mode. Note that when the WDT is initialized as a time-out reset timer, WDTR and WIDPD have no effect.

1. Device is powered on --> Software code is executed and WDT starts counting. The timeout interval is configured by WDPS[2:0] (WDCON[2:0]).

2. The configured timeout event occurs –> WDT will set the interrupt flag WDTF (WDCON.5).

3. If the WDT interrupt enable bit EWDT (EIE.4) and the global interrupt enable EA are both set, the WDT interrupt routine is executed.

4. If the system is in normal operation, during the 512 LIRC clock delay, the system can clear the counter by setting WDCLR to avoid the system being reset by WDT.

5. If no 1 is written to WDCLR within these 512 LIRC clocks, a WDT reset will occur.

6. Set the WDCLR bit to clear the WDT counter.

7. If the system operates normally, this bit is self-clearing.

8. Once a WDT reset occurs, the WDT reset flag WDTRF (WDCON.3) will be set. This bit will remain unchanged after any reset except a power-on reset.

9. The user can clear WDTRF through software. Note that all bits of WDCON have write timing requirements.

Note: The WDT counter requires special attention. The hardware will automatically clear the WDT counter and prescaler value after the following events occur:

(1) Entering idle or power-down mode, or being awakened from idle or power-down mode

(2) Reboot. It can prevent unpredictable system reboots.

2.1 The main application of the watchdog timer reset is system monitoring, which is very important for real-time control systems. In some power interference, electromagnetic interference, the CPU may execute wrong code, or enter an uncontrollable state. If these situations are not controlled, the system may crash.

2.2 Using the Watchdog Timer The user can select the ideal “feed the watchdog” time to clear the WDT counter.

2.3 By setting WDCLR through instructions, the program can continue to run without resetting the watchdog timer. If interference causes the code to run in an incorrect state, resulting in the failure to clear the watchdog timer in time, it will cause the chip to reset and the system to recover from the incorrect state.

2.4 The following conditions will cause WDT reset failure, please avoid them. When CKDIV has a set value (not equal to 00H), it means that the system frequency division is effective. At this time, if you enter the power-down mode, the WDT reset will fail. It is recommended to use WKT wake-up for applications that wake up from power-down mode.

General purpose timer

Another application of the watchdog timer is to use it as a simple, long-period timer. When the CONFIG bit WDTEN[3:0] (CONFIG4[7:4]) is FH, the WDT is initialized as a general-purpose timer. In this mode, WDTR and WIDPD are accessible by software.

The watchdog timer starts running by setting WDTR to 1 and stops by clearing WDTR.

When the WDT configured time interval expires, the WDTF flag will be set. The WDTF flag can be queried by software to detect whether it has timed out.

If EWDT (EIE.4) and EA are set, WDT will generate an interrupt and then WDT will continue counting.

The user must clear WDTF and wait for the next overflow by polling the WDTF flag or waiting for an interrupt to occur.

In some low-power applications, to save power, the CPU is often in idle mode when no events are being processed.

By running timers 0~3, waking up periodically to see if there is a need to respond, the power consumption in this idle mode will reach the milliampere (mA) level. In order to reduce the power consumption to the microampere (μA) level, when there is no need to respond, the CPU should stay in power-down mode and can be woken up at programmed intervals.

N76E003 is equipped with a useful WDT wake-up function. Based on the internal 10kHz RC clock source, the watchdog timer has very low power consumption and can count and wake up the CPU in power-down mode.

Sample Code

/*---------------------------------------------------------------------------------------------------------*/

/* */

/* Copyright(c) 2016 Nuvoton Technology Corp. All rights reserved. */

/* */

/*---------------------------------------------------------------------------------------------------------*/

//***********************************************************************************************************

// Nuvoton Technoledge Corp. 

// Website: http://www.nuvoton.com

// E-Mail : MicroC-8bit@nuvoton.com

// Date : Apr/21/2016

//***************************************************************************************************************#define set_WIDPD BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT4;EA=BIT_TMP;//***************************************************************************************************************

// File Function: N76E003 Watch Dog as pure timer with interrupt demo code

//***********************************************************************************************************

#include "N76E003.h"

#include "Common.h"

#include "Delay.h"

#include "SFR_Macro.h"

#include "Function_define.h"

/************************************************************************************************************

* WDT interrupt sub-routine

********************************************************************************************************************/

void WDT_ISR (void) interrupt 10

{

                    //---------toggle GPIO1---------    

                        clr_GPIO1; Timer0_Delay1ms(50);

                        set_GPIO1; Timer0_Delay1ms(50);

                        clr_GPIO1; Timer0_Delay1ms(50);

                        set_GPIO1; Timer0_Delay1ms(50);

                    //---------end toggle GPIO2--------

                        clr_WDTF;

                        set_WDCLR;

}

/************************************************************************************************************

* Main function 

********************************************************************************************************************/

void main (void)

{

/* Note

  WDT timer base is LIRC 10Khz

*/

  Set_All_GPIO_Quasi_Mode;

                        clr_GPIO1; Timer0_Delay1ms(500);

                        set_GPIO1; Timer0_Delay1ms(500);

                        clr_GPIO1; Timer0_Delay1ms(500);

                        set_GPIO1; Timer0_Delay1ms(500);

//WDT init

//--------------------------------------------------------

//Warning:

//Pleaes always check CONFIG WDT disable first 

//only when WDT reset disable, WDT use as pure timer

//--------------------------------------------------------

      TA=0xAA;TA=0x55;WDCON=0x07; //Setting WDT prescale 

        set_WDTR; //WDT run

        set_WDCLR; //Clear WDT timer

        set_EWDT;

        EA =1;

#if 0

    while(1);

#else

        set_WIDPD; //WDT run in POWER DOWM mode setting if needed

        while (1)

        {

            set_PD;

                    //---------toggle GPIO1---------    

                        clr_P04; Timer1_Delay10ms(5);

                        set_P04; Timer1_Delay10ms(5);

                        clr_P04; Timer1_Delay10ms(5);

                        set_P04; Timer1_Delay10ms(5);

                    //---------end toggle GPIO1---------

        }

#endif

}