[C51 Getting Started Notes] IIC bus + E2PROM chip (24C02)

Common bus technologies:

The use of serial bus technology can greatly simplify the hardware design of the system, reduce the size of the system, and improve reliability. At the same time, the system can be easily modified and expanded.

Commonly used serial expansion buses include: I2C (Inter IC BUS) bus, single bus (1-WIRE BUS), SPI (Serial Peripheral Interface) bus and Microwire/PLUS.

IIC bus overview:

I2C bus is a high-performance serial bus launched by PHLIPS, which has bus arbitration and high-speed and low-speed device synchronization functions.

Bus arbitration: All mounted devices have their own addresses, and the function of distinguishing devices by addresses is called bus arbitration.

The I2C bus is connected to the positive power supply through a pull-up resistor (usually 10K). When the bus is idle, both lines are high. A low level output by any device connected to the bus will make the bus signal low, that is, the SDA and SCL of each device

They are all linear “and” relationships.

Receiver and Transmitter:

Each device connected to the I2C bus has a unique address. Data transmission between the host and other devices can be done by the host sending data to other devices. In this case, the host is the transmitter. The device receiving data on the bus is the receiver.

Multi-host processing:

In a multi-host system, there may be several hosts trying to start the bus to transfer data at the same time. To avoid confusion, the I2C bus must go through bus arbitration to decide which host controls the bus.

In C51:

In the serial bus expansion of the 80C51 single-chip microcomputer application system, we often encounter a single-host situation with the 80C51 single-chip microcomputer as the host and other interface devices as slaves.

data transmission:

Data bit validity:

When the I2C bus is transmitting data, the data on the data line must remain stable while the clock signal is at a high level. The high or low level state of the data line is allowed to change only when the signal on the clock line is at a low level.

Start and stop signals

When the SCL line is at a high level, the change of the SDA line from a high level to a low level indicates a start signal;

When the SCL line is at a high level, the change of the SDA line from a low level to a high level indicates a termination signal.

Both the start and stop signals are sent by the host. After the start signal is generated, the bus is in an occupied state; after the stop signal is generated, the bus is in an idle state.

If the device connected to the I2C bus has a hardware interface for the I2C bus, it is easy to detect the start and end signals.

After receiving a complete data byte, the receiving device may need to complete some other work, such as processing internal interrupt services, and may not be able to receive the next byte immediately. At this time, the receiving device can pull the SCL line to a low level, so that the host is in a waiting state. When the receiving device is ready to receive the next byte, the SCL line is released to a high level, so that data transmission can continue. (Pull it down manually to make the host wait)

Data transmission format:

(1) Byte transmission and response

 Each byte must be 8 bits long. When data is transmitted, the most significant bit (MSB) is transmitted first, and each transmitted byte must be followed by an acknowledge bit (i.e., a frame has a total of 9 bits).

Answer the question:

When the slave does not respond to the host addressing signal, it must set the data line to a high level, and the host generates a termination signal to end the data transfer on the bus.

When the slave responds to the master but cannot receive more data after a period of data transmission, the slave can notify the master by "non-response" to the first data byte that cannot be received, and the master should send a termination signal to end the continued data transmission.

When the master receives data, it must send a signal to the slave to end the transmission after receiving the last data byte. This signal is achieved by a "non-response" to the slave. Then, the slave releases the SDA line to allow the master to generate a termination signal. (This signal: non-response to the slave)

Data frame format:

The IIC data signal is broad in nature, including both address signals and real data signals.

After the start signal, a slave address (7 bits) must be transmitted, and the 8th bit is the data transmission direction bit (R/T). "0" indicates that the host sends data (T), and "1" indicates that the host receives data (R).

Each data transfer is always terminated by a termination signal generated by the host. However, if the host wishes to continue to occupy the bus for new data transfer, it can not generate a termination signal, and immediately send a start signal again to address another slave. (Do not terminate, directly start addressing here)

Bus addressing:

The I2C bus protocol has clear provisions: use a 7-bit addressing byte (the addressing byte is the first byte after the start signal).

D7 to D1 constitute the slave address. D0 is the data transfer direction bit. When it is "0", it means the host writes data to the slave, and when it is "1", it means the host reads data from the slave.

When the host sends an address, each slave on the bus compares the 7-bit address code with its own address. If they are the same, it believes that it is being addressed by the host and identifies itself as a transmitter or receiver based on the R/T bit.

Slave address:

It consists of a fixed part and a programmable part. In a system, you may want to connect multiple identical slaves. The programmable part of the slave address determines the maximum number of devices of this type that can be connected to the bus. For example, if 4 of the 7-bit addressing bits of a slave are fixed bits and 3 are programmable bits, then only 8 identical devices can be addressed, that is, 8 identical devices can be connected to the I2C bus system.

Using 80C51 to simulate IIC: (Signal simulation combining software and hardware)

Typical signal simulation: In order to ensure the reliability of data transmission, the data transmission of the standard I2C bus has strict timing requirements. The simulation timing of the start signal, stop signal, sending "0" and sending "1" of the I2C bus; (the microcontroller needs to simulate the timing of IIC)

How to simulate:

Expansion of I2C bus devices:

Devices:

AT24C series E2PROM chip writing process:

The fixed part of the address of the AT24C series E2PROM chip is 1010. The A2, A1, and A0 pins are connected to high and low levels to obtain a certain 3-bit code. The 7-bit code formed is the address code of the device.

When the microcontroller performs a write operation:

First, send the device's 7-bit address code and write direction bit "0" (a total of 8 bits, i.e. one byte)

After sending, release the SDA line and generate the 9th clock signal on the SCL line.

After the selected memory device confirms that it is its own address, it generates a response signal on the SDA line.

After receiving the response, the microcontroller can transmit data.

Data transfer

The microcontroller first sends a byte of the first address of the storage area to be written into the device.

After receiving the response from the memory device, the microcontroller sends each data byte one by one, but waits for the response after each byte is sent.

Note: The on-chip address of the AT24C series device will automatically increase by 1 after receiving each data byte address. Within the limit of the chip's "number of bytes loaded at one time" (different chips have different byte numbers), you only need to enter the first address. When the number of loaded bytes exceeds the chip's "number of bytes loaded at one time", the data address will be "rolled up" and the previous data will be overwritten. (The data will be automatically filled into the memory, and will be overwritten from the beginning after it is filled)

When the microcontroller performs a read operation:

24C02 chip:

E0E1E2: Programmable bits of address

WP: Write Protect (Continue 1 Write Protect)

SCL SDA：IIC

code：

//Memory of power-on times

#include

#include

#define uchar unsigned char 

#define uint unsigned int 

unsigned char code smg_du[]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0x77,0x7c,0x39,0x5e,0x79,0x71,0x00};

//Initialize SDASCL

sbit sda=P2^1;

sbit scl=P2^0;

void init(void); //initialization

void start(void); //Start signal

void stop(void); //Termination signal

void ack(void); //Response signal

void noack(void); //non-acknowledge signal

void iicwr_byte(uchar dat); //write a byte

uchar iicre_byte(void); //read a byte

void delay (void); //short delay function

void delay1(void); //long delay function

//Function encapsulation

void write_byte(uchar add,uchar dat);

fly read_byte(fly add);

void init(void)

{

sda=1;

scl=1;

}

void delay1(void)

{

uint a=30000;

while(a--);

}

void delay(void)

{

//cpu empty operation

_nop_();_nop_();_nop_();_nop_();

_nop_();_nop_();_nop_();_nop_();

}

void start(void)

{

//SDA falling edge when SCL is high

//heat

sda=1;

delay();

scl=1;

delay();

//Falling edge

sda=0;

delay();

}

void stop(void)

{

//SCL high level SDA low level SDA rising edge

//heat

sda=0;

delay();

scl=1;

delay();

//Rising edge

sda=1;

delay();

}

void ack(void)

{

flying i;

//Sent by the microcontroller, so the microcontroller needs to receive this signal

//Simulation timing diagram

//SCL keeps 1 for a while

scl=1;

delay();

//Waiting: When SDA is reflected or times out, it is considered to be answered

while((sda==1)&&(i<200))i++;

scl=0;

delay();

}

void noack(void)

{

//Simulation timing diagram

sda=1;

delay();

scl=1;

delay();

scl=0;

delay();

}

void iicwr_byte(float dat)

{

flying i;

// Only when SCL is low can the data be changed. Prepare the data first and then pull SCL high

scl=0;

for(i=0;i<8;i++)

{

if(dat&0x80)// dat&1000 0000 The result is 1. The result of write operation is 0. The result of read operation is

{

sda=1;

}

else 

{

sda=0;

}