Exynos4412 bare metal development - interrupt handling

Take KEY2 controlling LED3 on and off as an example:

1. Polling method

【0】Detect button k2. When button k2 is pressed once, LED2 flashes once.

【1】Check the schematic diagram, connect the pins and control logic
(1) Push button K2 is connected to the GPX1_1 pin
(2) Control logic
       K2 is pressed ---- K2 is closed ---- GPX1_1 is low voltage
       K2 is normal ---- K2 is open ---- GPX1_1 is high voltage

【2】Check the corresponding chip manual

    【2-1】Cyclic detection of the input level of the GPX1_1 pin. When the voltage is low, the button is pressed.

        (1) Configure the GPX1_1 pin function as input and set the internal pull-up and pull-down to disable.
                  GPX1.CON = GPX1.CON &(~(0xf<<4)) ;

                  GPX1.PUD = GPX1.PUD & ~(0x3 << 2);
　　(2) Loop detection:

1. while(1)  

2. {  

3.     if(!(GPX1.DAT & (0x1<<1))) // Returns true, the button is pressed  

4.     {      

5.         msdelay(10);  

6.         if(!(GPX1.DAT & (0x1<<1))) //Secondary detection, debounce  

7.         {  

8.             GPX2.DAT |= 0x1 << 7; //Turn on LED2  

9.             mydelay_ms(500);  

10.             GPX2.DAT &= ~(0x1<<7); //Turn off LED2  

11.             mydelay_ms(500);  

12.         

13.             while(!(GPX1.DAT & (0x1<<1)));  

14.         }  

15.     }  

16. }  

This polling method always occupies the CPU and is not conducive to operation.

2. Interrupt Mode

When K2 is pressed, the level obtained by the GPX1_1 pin is regarded as an abnormal event. Enable exception handling, and respond to exception handling every time k2 is pressed. The SPI transfer process is shown as follows:

Note:

      The Exynos4412 interrupt controller includes 160 interrupt control sources, which come from soft interrupts (SGI), private external interrupts (PPI), and public external interrupts (SPI).

      Exynos4412 uses GIC interrupt controller, mainly because Contex-A9 is a multi-core processor. GIC (Generic Interrupt Controller) is used to select which CPU interface to use. It has two main functions:

1) Distributor: Set a switch to determine whether to receive an external interrupt source; select the CPU interface for the interrupt source;

2) CPU interface: Set a development to determine whether to accept the interrupt source request;

The specific implementation is as follows:

1. Peripheral level 1---Set up GPIO controller

1-- Disable the pull-up and pull-down of the GPX1_1 pin

        GPX1PUD[3:2]= 0b00;

2 -- Set the GPX1_1 pin function to interrupt function WAKEUP_INT1[1] --- EXT_INT41[1]

        GPX1CON[7:4] = 0xf

3 -- EXT_INT41CON configures the trigger level

       Currently configured as falling edge trigger:

       EXT_INT41CON[6:4] = 0x2

4 -- EXT_INT41_FLTCON0 configures interrupt pin filtering

       It is enabled by default and does not require configuration.

5 -- EXT_INT41_MASK interrupt enable register

      Enable INT41[1]

      EXT_INT41_MASK[1] = 0b0

6 -- EXT_INT41_PEND interrupt status register
       When the GPX1_1 pin receives an interrupt signal, an interrupt occurs, and the corresponding bit of the interrupt status register EXT_INT41_PEND is automatically set to 1.
        Note: When the interrupt processing is completed, the corresponding status bit needs to be cleared. Set 1 to clear 0.
        EXT_INT41_PEND[1] =0b1 

2. Interrupt Controller

1-- Find the name of the peripheral interrupt and the corresponding name of the GIC interrupt controller

   　Check the chip manual (this example: Exynos_4412 -- Table 9.2)
       WAKEUP_INT1[1] --- EXT_INT41[1] --- INT[9] --- SPI[25]/ID[57]

      It corresponds to INT[9], and the interrupt ID is 57. This is very important and plays a big role in the subsequent register settings;

The following is the specific process of peripheral and interrupt controller processing:

2 -- GIC enabled

       ICDDCR =1;

       Enable the allocator.

3 -- Enable the corresponding interrupt to the distributor

      ICDISER.ICDISER1 |= (0x1 << 25); //57/32 =1...25 Get the integer (which register) and the remainder (which bit)

      ICDISER is used to enable the corresponding interrupt to the distributor. One bit controls one interrupt source. One ICDISER can control 32 interrupt sources. Here, the interrupt ID corresponding to INT[9] is 57, so it is set in ICDSER1. 57/32 = 1 remainder 25, so here the 25th position of ICDISER1 is set to 1.

4 -- Select CPU interface

      Set SPI[25]/ID[57] to be handled by which CPU, currently set to IRQ interrupt of cpu0

      ICDIPTR.ICDIPTR14 |= 0x01<<8; //SPI25 interrupts are sent to processor 0 //57/4 = 14..1 [15:8] of register 14

      Each 8 bits of the ICDIPTR register controls an interrupt source

5 -- Globally enable cpu0 interrupt processing

       CPU0.ICCICR |= 0x1;

       Enable interrupt to CPU.

6 -- Priority mask register, set cpu0 to handle all interrupts.

      CPU0.ICCPMR = 0xFF;

3. ARM core (cpu0)

       After setting the first two steps, you can wait for the interrupt to occur. When the interrupt occurs, the ARM core processes as follows:

 1-- Four major steps and three minor steps--- Hardware

      (1) Copy CPSR to SPSR_
　 (2) Set appropriate CPSR bits:                                
　　　　(2-1) - Change processor state to ARM state
 　　　   (2-2) - Change processor mode to corresponding exception mode
 　　　   (2-3) - Set interrupt disable bit to disable corresponding interrupt (if necessary)
　 (3) Save return address to LR_
　 (4) Set PC to corresponding exception vector
       　　　

2 -- Interrupt service routine --- start.S assembly

1. .text  

2. .global _start  

3. _start:  

4.         b reset  

5.         ldr pc,_undefined_instruction  

6.         ldr pc,_software_interrupt  

7.         ldr pc,_prefetch_abort  

8.         ldr pc,_data_abort  

9.         ldr pc,_not_used  

10.         ldr pc,_irq  

11.         ldr pc,_fiq  

12.   

13. _undefined_instruction: .word _undefined_instruction  

14. _software_interrupt: .word _software_interrupt  

15. _prefetch_abort: .word _prefetch_abort  

16. _data_abort: .word _data_abort  

17. _not_used: .word _not_used  

18. _irq: .word irq_handler  

19. _fiq: .word _fiq  

20.   

21.   

22. reset:  

23.   

24.     ldr r0,=0x40008000  

25.     mcr p15,0,r0,c12,c0,0 @ Vector Base Address Register  

26.   

27.   

28. init_stack:  

29.         ldr r0,stacktop /*get stack top pointer*/  

30.   

31.     /********svc mode stack********/  

32.         mov sp,r0  

33.         sub r0,#128*4 /*512 byte for irq mode of stack*/  

34.     /****irq mode stack**/  

35.         msr cpsr,#0xd2  

36.         mov sp,r0  

37.         sub r0,#128*4 /*512 byte for irq mode of stack*/  

38.     /***fiq mode stack***/  

39.         msr cpsr,#0xd1  

40.         mov sp,r0  

41.         sub r0,#0  

42.     /***abort mode stack***/  

43.         msr cpsr,#0xd7  

44.         mov sp,r0  

45.         sub r0,#0  

46.     /***undefine mode stack***/  

47.         msr cpsr,#0xdb  

48.         mov sp,r0  

49.         sub r0,#0  

50.    /*** sys mode and usr mode stack ***/  

51.         msr cpsr,#0x10  

52.         mov sp,r0 /*1024 byte for user mode of stack*/  

53.   

54.         b main  

55.   

56.     .align 4  

57.   

58.     /**** swi_interrupt handler ****/  

59.   

60.   

61.     /**** irq_handler ****/  

62. irq_handler:  

63.   

64.     sub lr,lr,#4  

65.     stmfd sp!,{r0-r12,lr}  

66.     .weak do_irq  

67.     bl do_irq  

68.     ldmfd sp!,{r0-r12,pc}^  

69.   

70. stacktop: .word stack+4*512  

71. .data  

72.   

73. stack: .space 4*512  

3--Interrupt handler--- do_irq function C language (function prototype void name(void))

(1) Read the interrupt ID register (ICCIAR) being processed

          irq_num = (CPU0.ICCIAR & 0x1FF);

(2) According to irq_num, branch to handle interrupt  

1. switch(irq_num)  

2. {  

3.     .  

4.     case 57:  

5.         break;  

6.     ....  

7.   

8. }  

 (3) Clear the interrupt status bit

        (3-1) i. Peripheral level, EXT_INT41_PEND |= 0x1 << 1;
        (3-2) ii. GIC level, ICDICPR.ICDICPR1 |= 0x1 << 25;
        (3-3) iii. CPU0 level CPU0.ICCEOIR = (CPU0.ICCEOIR & ~(0x1FF)) | irq_num;

Here is the C program:

1. #include "exynos_4412.h"  

2. #include "led.h"  

3.   

4. void delay_ms(unsigned int num)  

5. {  

6.     int i,j;  

7.     for(i=num; i>0;i--)  

8.     for(j=1000;j>0;j--)  

9.         ;  

10. }  

11. void do_irq(void)  

12. {  

13.     static int a = 1;  

14.     int irq_num;  

15.     irq_num = CPU0.ICCIAR&0x3ff; //Get the interrupt number  

16.     switch(irq_num)  

17.     {  

18.     case 57:  

19.         printf("in the irq_handlern");  

20.             if(a)  

21.                 led_on(1);  

22.             else  

23.                 led_off(1);  

24.             a = !a;  

25.             EXT_INT41_PEND = EXT_INT41_PEND |((0x1 << 1)); // Clear GPIO interrupt flag  

26.             ICDICPR.ICDICPR1 = ICDICPR.ICDICPR1 | (0x1 << 25); // Clear GIC interrupt flag  

27.         break;  

28.     }  

29.     CPU0.ICCEOIR = CPU0.ICCEOIR&(~(0x3ff))|irq_num; //Clear CPU interrupt flag  

30. }  

31. /* 

32.  * Bare metal code, different from the LINUX application layer, must add loop control 

33.  */  

34. int main (void)  

35. {  

36.     GPX1.CON =GPX1.CON & (~(0xf << 4)) |(0xf << 4); //Configure the pin function as external interrupt  

37.     GPX1.PUD = GPX1.PUD & (~(0x3 << 2)); //Turn off the pull-up and pull-down resistors  

38.     EXT_INT41_CON = EXT_INT41_CON &(~(0xf << 4))|(0x2 << 4); //External interrupt trigger mode  

39.     EXT_INT41_MASK = EXT_INT41_MASK & (~(0x1 << 1)); // Enable interrupt  

40.     ICDDCR = 1; // Enable the distributor  

41.     ICDISER.ICDISER1 = ICDISER.ICDISER1 | (0x1 << 25); // Enable the corresponding interrupt to the distributor  

42.     ICDIPTR.ICDIPTR14 = ICDIPTR.ICDIPTR14 & (~(0xff << 8))|(0x1 << 8); //Select CPU interface  

43.     CPU0.ICCPMR = 255; //Interrupt mask priority  

44.     CPU0.ICCICR = 1; // Enable interrupt to CPU  

45.     led_init();  

46.     while(1)  

47.     {  

48.   

49.     }  

50.    return 0;  

51. }  

52.