ARM Architecture and Programming Notes

Basic concepts of memory mapping

The address generated by the ARM processor is called a virtual address. The method of converting this virtual address to another physical address according to a certain rule is called address mapping. This physical address represents the location of the memory being accessed. It is an address range within which program code can be written.

Necessity of memory map control

In order to allow programs running in different memory spaces to control exceptions, the exception vector tables located in different memory spaces can be remapped to fixed addresses 0x00 to 0x3F through memory mapping control to achieve source control of the exception vector table.

APCS specifies the basic rules for subroutine calling, including the usage of registers and data stacks during subroutine calling and the passing of parameters.

Exception Vector Table

For each exception event, there is a corresponding handler, which are associated and stored in a fixed unit of the memory in the format of a one-dimensional table. This table that specifies the correspondence between each exception interrupt and its handler is called the exception vector table.

ARM processor's response process to abnormal interrupt

(1) Save the current state of the processor, the interrupt mask bit, and each condition flag bit.

(2) Set the corresponding bit in the current program status register CPSR.

(3) Set register lr_mode to the return address.

(4) Set the program counter value (PC) to the interrupt vector address of the interrupt, thereby jumping to the corresponding exception interrupt handler for execution.

Abnormal response process

Except for reset exceptions, when an exception occurs, the ARM core will try to execute the current instruction as much as possible, and then automatically perform the following actions:

(1) Save the return address to LR_

(2) Copy CPSR to SPSR_.

(3) Set CPSR to enter the corresponding processor mode.

(4) Set bit 7 of CPSR to disable IRQ. If the exception is a fast interrupt or reset, then bit 6 of CPSR must also be set to disable fast interrupt.

(5) Force the vector address value to be assigned to PC.

Entering an exception

1. Save the address of the next instruction in the appropriate LR; 2. Copy the CPSR to the appropriate SPSR; 3. Force the CPSR mode bits to be set to the value corresponding to the exception type; 4. Force the PC to fetch the instruction from the associated exception vector.

Exit abnormally

1. Subtract the offset from the value in LR (R14) and store it in PC. The offset varies depending on the type of exception. 2. Copy the value of SPSR back to CPSR. 3. Clear the interrupt disable flag set at the entry.

ARM processor exceptions are divided into seven types: ① data abort ② fast interrupt request ③ normal interrupt request ④ prefetch abort ⑤ software interrupt ⑥ reset ⑦ undefined instruction exception.

The program jump in the exception vector table uses the LDR instruction instead of the B instruction. Reason:

1. The LDR instruction can jump to the full address range, while the B instruction can only jump within the range of 32MB before and after;

2. The chip has a memory remapping function. When the vector table is located in the internal RAM or external memory, the B instruction cannot jump to the correct location.

Little-endian memory system:

In the little-endian format, the high-order digits are stored in the high-order bytes. Therefore, memory system byte 0 is connected to data lines 7-0 (low-order aligned).

Big-endian memory systems:

In the big-endian format, the high-order digits are stored in the low-order bytes. Therefore, memory system byte 0 is connected to data lines 31-24 (high-order aligned).

STMFD sp!,{lr};Save data stackLDMFD sp!,{pc};Restore

Reset: When the nRESET signal becomes high again, the ARM processor performs the following operations:

1. Force M[4:0] in CPSR to b10011 (supervisory mode); 2. Set the I and F bits in CPSR; 3. Clear the T bit in CPSR; 4. Force the PC to fetch the next instruction starting from address 0x00; 5. Return to ARM state and resume execution.

R14 (LR) register and subroutine call

1. Program A calls program B during execution;

2. The program jumps to label Lable and executes program B. At the same time, the hardware stores the address of the next instruction of the "BL Lable" instruction in R14 (LR);

3. At the end of program B execution, the content of register R14 is placed in PC and the program returns to program A;

ARM processors have 7 operating modes:

① User mode: non-privileged mode, which is the mode in which normal programs are executed. Most tasks are executed in this mode. In user mode, if no exception occurs, the application is not allowed to change the processor's working mode on its own. If an exception occurs, the processor will automatically switch the working mode.

②FIQ mode: also known as fast interrupt mode, supports high-speed data transmission and channel processing. This mode will be entered when a high priority (fast) interrupt occurs.

③IRQ mode: also known as normal interrupt mode, this mode is entered when a low priority (normal) interrupt occurs. In this mode, there are two types of interrupts: vector interrupts and non-vector interrupts. Normal interrupts are performed in IRQ mode.

④SVC mode: It is called management mode, which is an operating system protection mode. The processor enters this mode when a reset or soft interrupt instruction is executed.

⑤ Abort mode: When access is abnormal, the system will enter the abort mode to handle memory failures, implement virtual storage or storage protection.

⑥ Undefined instruction exception mode: This mode is entered when an undefined instruction is executed. It is mainly used to handle undefined instruction traps and support software emulation of hardware coprocessors, because undefined instructions mostly occur in coprocessor operations.

⑦ System mode: A privileged mode that uses the same register set as User mode and is used to run privileged-level operating system tasks.

Difference: Privileged mode--the program can access all system resources and can switch processor modes at will.

ARM9 uses a 5-stage pipeline: instruction fetch, decoding, execution, memory access, and register write back.

Instruction fetch: Read instructions from the instruction cache.

Decode: Decode the instruction, identify which register to operate on and read the operand from the general register.

Execute: Perform ALU operations and shift operations. If the instruction is for memory operation, the memory address to be accessed is calculated in the ALU.

Memory access: If it is an instruction to access the memory, it is used to implement the data buffering function (through the data cache); if it is not an instruction to access the memory, this level of the pipeline is an empty clock cycle.

Register write back: Write the instruction operation or operation result back to the target register.

CISC: Complex Instruction Set Computer

It has a large number of instructions and addressing modes, and the instruction length is variable; 8/2 principle: 80% of programs use only 20% of the instructions; most programs can run using only a small number of instructions.

RISC: Reduced Instruction Set Computer

Contains only the most useful instructions, with fixed instruction length; ensures that the data channel executes each instruction quickly; makes CPU hardware structure design simpler

1. Both the MOV instruction and the LDR instruction transfer data to the target register, but is there any difference between them?

   The MOV instruction is used to transfer data from one register to another, or to transfer a constant to a register, but it cannot access memory. The LDR instruction is used to read data from memory and put it into a register.

1. What do the letters of ARM7TDMI-S stand for? What are the core features? How many pipeline stages does it use?

ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{-S}

The letters in the curly brackets are optional and have the following meanings:

x ——series number, such as "7" in ARM7, "9" in ARM9;

y - internal memory management/protection unit, such as "2" in ARM72 and "4" in ARM94;

z ——contains cache;

T——supports 16-bit Thumb instruction set;

D ——Support JTAG on-chip debugging;

M - supports ARM instructions for long multiplication operations (64-bit result), including fast multiplier;

I -- debug hardware with embedded trace macro ETM (Embedded Trace Macro) for setting breakpoints and watchpoints;

E ——Enhanced DSP instructions (based on TDMI);

J - Contains the Java accelerator Jazelle, which makes Java code run eight times faster and reduces power consumption to 80% of the original compared to the Java virtual machine;

F ——vector floating point unit;

S - Synthesizable version, which means the processor core is provided in source code form. This source code form can be compiled into a form that is easy to use with EDA tools.

Kernel features:

32/16-bit RISC architecture (ARM v4T).

32-bit ARM instruction set with highest performance and flexibility.

Code-compact 16-bit Thumb instruction set.

Unified bus interface, instructions and data are transmitted on a 32-bit bus.

3-stage pipeline.

32-bit Arithmetic Logic Unit (ALU).

Extremely small core size and low power consumption.

Coprocessor interface.

Extended debugging facilities: · EmbeddedICE-RT real-time debugging unit. · JTAG interface unit. · Interface for direct connection with the Embedded Trace Macrocell (ETM).

The ARM7 series core adopts a three-stage pipeline core structure, which includes fetch, decode, and execute.

Instruction fetch: fetch the instruction from the memory and put it into the instruction cache.

Decoding: This is done by the decoding logic unit, which interprets the instructions in the previous instruction cache and tells the CPU how to operate.

·Execution: This stage includes shift operations, reading general register contents, outputting results, writing general registers, etc. That is, the instructions that have been decoded in the previous step are implemented in logic circuits.