ATmega32 Status Register

The status register contains information about the results of the most recently executed arithmetic instruction. This information can be used to change the program flow to implement conditional operations. As described in the instruction set, all ALU operations will affect the contents of the status register. This eliminates the need for dedicated comparison instructions in many cases, making the system run faster and the code more efficient.

The status register will not be automatically saved when entering the interrupt service routine, nor will it be automatically restored when the interrupt returns. These tasks need to be handled by software.

The AVR interrupt register SREG is defined as follows:
· Bit 7 – I: Global interrupt enable
I enables global interrupts when set. Individual interrupt enable is controlled by other independent control registers. If I is cleared, no interrupt will be generated
regardless whether the individual interrupt flag is set or not. I is cleared after any interrupt occurs, and
I is set again to enable interrupts after executing the RETI instruction. I can also be set and cleared by the SEI and CLI instructions.
· Bit 6 – T: Bit copy storage
The bit copy instructions BLD and BST use T as the destination or source address. BST copies a bit of a register to T, while
BLD copies T to a bit of a register.
· Bit 5 – H: Half carry flag The half carry flag H indicates that a half carry has occurred in an arithmetic operation. This flag is very useful for BCD operations. See the description of
the instruction set for details . ·Bit 4 – S: Sign bit, S = N ⊕ V S is the exclusive OR of the negative flag N and the 2’s complement overflow flag V. See the instruction set description for details. ·Bit 3 – V: 2’s complement overflow flag supports 2’s complement operations. See the instruction set description for details. ·Bit 2 – N: Negative flag indicates that the result of an arithmetic or logical operation is negative. See the instruction set description for details. ·Bit 1 – Z: Zero flag indicates that the result of an arithmetic or logical operation is zero. See the instruction set description for details. ·Bit 0 – C: Carry flag indicates that a carry occurred in an arithmetic or logical operation. See the instruction set description for details.