ATmega48 SPI data mode and timing-EEWORLD

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ATmega48 has four XCKn (SCK) phase and polarity combinations related to serial data, which are determined by UCPHAn and UCPOLn. See Figure 77 for the timing diagram of data transmission. The shifting out and locking of data bits occur on the opposite edge of the XCKn signal to ensure that there is enough time for the data to stabilize. The functions of UCPOLn and UCPHAn are summarized in Table 86. Changing the settings of these two bits will disrupt ongoing communications.

ATmega48 UCPOLn and UCPHAn functions

ATmega48 UCPHAn and UCPOLn data transmission timing diagram

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