STM8S special topic: ADC data conversion

Introduction

Digital signals are discrete signals, and analog signals are continuous signals. If a digital circuit needs to process an analog signal, a signal conversion system is required. Conversely, analog circuits also need to perform signal conversion to process digital signals.

The A/D and D/A converters are the bridges for processing the two signals.

Common A/D converters include parallel comparison type, successive approximation type, VF type, double integral type, etc.

Common D/A converters include weighted resistor network type, inverted T-type resistor network type, weighted capacitor network type, weighted current type, switch tree structure type, etc.

principle

system framework

Different STM8S microcontroller models have different ADC resources. Taking ADC2 as an example, ADC2 is a 10-bit successive approximation A/D converter that can provide 16 input channels.

The above figure is the structure diagram of A/D conversion, with signal input on the left, signal conversion in the middle, and signal output on the right. The core part is the intermediate signal conversion, with 3 configuration lines below.

ADON (ADC_CR1) is for power-on wake-up/conversion start. The first time it is set to 1, it wakes up the ADC. The second time it is set to 1, it starts the conversion. The second time it is set to 0, it shuts down the ADC.

CONT (ADC_CR1) is single/continuous conversion, set to 0 for single conversion, set to 1 for continuous conversion.

CH[3:0] (ADC_CSR) is the analog signal input channel selection, and the configuration value corresponds to AIN0~AIN15.

There are three trigger signals to start ADC conversion: software trigger (ADON), TIM1 timer trigger signal (TRGO), and external pin trigger (ADC_ETR).

The AD conversion related pins are described as follows:

Conversion Mode

The ADC1 advanced AD converter supports five conversion modes: single mode, continuous mode, continuous mode with buffer, single scan mode, and continuous scan mode.

ADC2 general AD converter supports single and continuous modes.

Single mode

Suitable for converting different channels one by one.

First, select the input channel, configure the CONT bit to 0, and the ADON bit to 1 to start the conversion. After the conversion is completed, the conversion end flag EOC (ADC_CSR) is set to 1, and the data is stored in the ADC data register. If the conversion end interrupt EOCIE (ADC_CSR) is enabled, an interrupt request is generated.

The ADC single conversion timing is as follows:

Continuous conversion

Suitable for continuous conversion of selected channels.

The ADC continuous conversion timing is as follows:

First, select the channel, set CONT to 1 to start the continuous conversion mode. After power-on, set ADON to 1 for the first time to wake up the conversion unit, delay for a period of time to stabilize the timing, set it to 1 again to start the conversion, and when the conversion is completed, EOC is set to 1. The data is cached in ADC_DR (need to be read in time, you can query EOC or interrupt reading). If the interrupt is enabled, a conversion end interrupt will be generated. Then the next conversion is automatically started. The EOC status bit needs to be cleared by software.

Conversion speed

The ADC conversion speed depends on the ADC clock frequency, which in turn depends on the system clock frequency and the ADC division factor. The division factor can be set using the SPSRL[2:0] (ADC_CR1) bits.

The ADC conversion requires 14 clock cycles, 3 samples, and 11 conversions.

Conversion accuracy

Taking ADC2 as an example, the resolution is 10 bits, and the analog channel input signal voltage is 5V, then the minimum voltage level is 5/2 times 10, and the resolution accuracy can reach 4.88mv. When the analog signal is higher than the IC reference voltage, a hardware voltage divider circuit needs to be designed.

register

Control Status Register ADC_CSR

Used for analog input channel selection, conversion end interrupt enable, and conversion end flag setting.

Control register 1ADC_CR1

Used for frequency division factor configuration, conversion mode configuration, power-on wake-up/conversion start configuration.

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Control register 2ADC_CR2

External trigger mode configuration, trigger enable configuration, data alignment configuration

The data converted by ADC is 10 bits and needs two registers to store.

Left justified: the upper 8 bits are written to ADC_DRH and the remaining bits are written to ADC_DRL.

Right justified: the lower 8 bits are written to ADC_DRL and the remaining bits are written to ADC_DRH.

process