ARM11 learning based on S3C6410 (XI) DDR initialization

     Previously, programs were run in the internal stepping stone. But the size of the stepping stone is very small. The size of ARM11 is only 8K. It is definitely not possible to run large programs in such a small space. So external memory is needed. The external memory of ARM11 uses DDR. So the DDR must be initialized and the code must be copied to the DDR.

     Let's first look at the S3C6410 booting with nandflash. When powered on, the CPU will automatically copy the first 8k data of the external nandflash to the internal stepping stone. The address of the stepping stone starts at 0x0c000000. Then the CPU maps the stepping stone to the address 0x00000000, and then jumps to address 0 to execute the first code.

Don't be confused by the 64M space of the stepping stone in the picture. It is actually not that big. It is only 8K in size. Because this space is very small, an external memory is needed. The picture also shows that the address of the external memory starts at 0x50000000. The total size can be 256M.

0x00000000~0x07FFFFFF corresponds to the internal mirror area. This area is used to mirror the boot code. Because S3C6410 supports multiple boot modes. When a peripheral storage device boot mode is selected, the first address of the storage device will be mapped to this area. In this way, when the CPU starts running the code from address 0, it is equivalent to running from the first address of the peripheral storage device.

0x08000000~ 0x0bFFFFFFF corresponds to the internal ROM, but the IROM is actually only 32KB. When you choose to boot from IROM, the first program to run is BL0, which is solidified by Samsung.

0x0c000000~ 0x0FFFFFFF corresponds to the internal SRAM, which is actually 8KB of Steppingstone.

0X10000000~0X3FFFFFFF corresponds to the main storage area, which is used to access devices on the external bus, such as oneNAND, NORFLASH. This area is divided into 6 banks. Each bank size is 128M. The maximum data width supports 16 bits. Each bank is selected by chip select xm0CS[0]~xm0CS[5].

0x50000000~0x6FFFFFFF. DRAM area. This area is divided into two areas, each occupying 256MB. It can be selected by chip select xm1CS[0] and xm1CS[1].

The ddr size of the OK6410 I use is 128M. The starting address starts at 0x50000000.

S3C6410 controls the operation of these storage devices through the controller. Because the memory driver is relatively troublesome, it is necessary to generate the corresponding timing to read and write the memory. If the CPU is allowed to control the generation of these timings, it will be a great burden for the CPU. Therefore, there is a memory controller in the chip. The CPU reads and writes data directly to the memory controller, and the memory controller automatically reads and writes the data to the memory according to the timing of the memory.

In this way, it is much easier for the CPU to access data. It only needs to send read/write signals, addresses, and data to the storage controller. The storage controller automatically goes to the external memory to fetch or write data.

 Because there are many external memories, it is difficult for a fixed memory controller to be compatible with all memories. Therefore, this memory controller must be configurable, and the control signal of the external memory must also meet fixed standards, that is, the timing must be the same, and the time interval can be different. Only in this way can they be unified. Therefore, the DDR initialization here is to configure the DDR memory controller. Let this memory control the external DDR memory.

 At this time, you need to read the data sheet of the external DDR memory to configure the DDR memory controller.

The above picture is the data sheet of DDR, the size is 64MB. OK6410 uses two chips, so the total size is 128M.

Next we need to configure the DDR controller.

The manual has a description of the order in which the DDR controller should be initialized. Therefore, when initializing the DDR controller, you must follow this prescribed order.

the entire process

1. Write 3'b100 to the MEMC_CMD register to put the DRAM controller into configuration state

2. Write memory timing parameters, chip configuration, and ID configuration registers. Please refer to the data sheet for details.

3. Wait 200us to allow DRAM to stabilize. This can be omitted because it has taken longer than this time since power-on.

4. Execute the memory initialization sequence

5. Write 3'b000 to the MEMC_CMD register to put the DRAM controller into the ready state

6. Check that the storage status of the MEMC_STAT register is 2'b01, indicating that it is ready.

The DRAM controller supports two types of dram, one is SDR and the other is DDR. The board uses DDR, so the execution memory initialization sequence in the above process is the execution of the DDR initialization sequence here.

1. Write 2'b11 to the command bit of the MEM_CMD register to make the DRAM controller generate a NOP command.

2. Write 2'b00 to the command bit of the MEM_CMD register to make the DRAM controller generate a precharge command

3. Write 2'b01 to the command bit of the MEM_CMD register to make the DRAM controller generate an automatic refresh command.

4. Write 2'b01 to the command bit of the MEM_CMD register to make the DRAM controller generate an automatic refresh command.

5. Write 2'b10 to the command bit of the MEM_CMD register to make the DRAM controller generate an MRS command. The backup address of EMRS must be set

6. Write 2'b10 to the command bit of the MEM_CMD register to make the DRAM controller generate an MRS command. The backup address of MRS must be set

Some of the parameters provided in the manual are incorrect. The actual values ​​should be referred to in the register description.

The following is the process for initialization

First use macro definitions to define the addresses

first step:

Write 3'b100 to the MEMC_CMD register to put the DRAM controller into configuration state

The above picture shows the description of this register. Only the lower three bits are useful. Write 100, which is 0x4.

Step 2:

Write memory timing parameters, chip configuration, ID configuration register. Here you need to refer to the data sheet.

Here you need to check the data sheet and set the registers.

 This is the time to set the refresh cycle. You can search the concept of DDR refresh cycle on Baidu.

In the manual, there is the following description

This means the refresh cycle is 7.8us. The value in the register setting is the refresh cycle, but this cycle is set by the number of clock cycles. If the clock cycle is 100ns, then the set value is 78, which is exactly 7.8us. In the previous clock initialization, this time was set to 133M. So you need to calculate how many clocks are needed. But here, just use the formula

7800 / ( 1000000000/133000000 ) + 1

The first number is the time to be set, in ns. The divided part indicates how many ns correspond to 133M clock. By calculating in this way, we can get how many clocks are needed to get 7.8us. The time is set later in this way, so we don't have to calculate.

This is to set the CAS parameters. Just set bits 3:1. The lowest bit is 0.

It is also stated in the data sheet that this parameter can be 2 or 3. It is set to 3 here.

This is to set the DQSS parameters

Also check the data sheet, in the timing section.

Data, here we look at the first two columns and the last column, the first column is the minimum, the second column is the maximum. The last one is the unit. Here it is in clocks, the minimum is 0.75 clocks. Here it can be set to 1.

This is to set the MRD parameters.

In the manual, the parameter is 2 clocks.

Here, the parameter is set to 2.

  Set RAS parameters.

  In the manual

 The parameter is 45ns, so we have to use the previous formula.

I won't explain it below. Just set all the timing parameters.

After configuring the P1T_ESR register, the timing is configured. Then configure the chip

Set bits 16, 4, 1, and 0 of this register to 1

Configure the read/write burst mode to 4.

The last 6 bits are used to configure the row and column number of the DDR. This is obtained from the DDR data sheet. The row is 13 and the column is 10. So the last 6 bits are 6'b010010, which is exactly 0x12.

This configuration has many bits. Mainly concerned with the configuration of the previous few.

Here, the configuration read delay [12:11] is 01, and the manual also says that this is used for mobile DDR SDRAM. The board uses mobile DDR. The memory type [10:8] is 011, indicating that the external memory is mobile DDR. The memory width [7:6] is set to 01, indicating that it is 32 bits. One DDR is 16 bits, but two pieces are spliced ​​together, so the width is 32 bits. I don't know what the settings of the following bits are used for yet.

This is the chip select setting for the chip. Since DRAM can have two, there are two registers corresponding to each. The board only uses one, which is chip0. So here only the first register is set.

When the address is 0x50000000, the DDR chip select should be valid so that the DRAM controller can access the DDR. The register [15:8] is this address. This means that this value is compared with the AXI address [31:24] bits to determine whether the chip is selected. So the 8-bit value here should be 0x50.

16 bits are the addressing method of the memory. The manual states that it is bank-row-column. So this bit should be 1.

For the lower 8 bits, the size of DDR is 128M. So the address space is

Here, the parameters are all set to 0. Minimum delay is selected.

The above has configured the DDR controller timing and chip configuration. The next step is to enter the memory initialization sequence.

Step 3: Memory Initialization Sequence

This is in sequence.

First issue the nop command.

Write 11 to bits [19:18]. Then the value written is 0x000c0000.