Timer 0 working mode 3

At this time, there are separate interrupts when the lower 8 bits and the upper 8 bits overflow

tl0 occupies T0

th0 occupies T1

The two counters are independent

/*

   Program function: timer0 verification program

   Version: v1

   Creation date: 2013.9.18

   creator:

 */

$NOMOD51 //Cancel the use of 51 internal default SFR

#include "REG8F301.INC"

dseg at 30h //General RAM byte segment starts at 30H

iseg at 80h //0-ffh address RAM segment 80h-ffh segment RAM can only be operated using indirect addressing

cseg at 0

        org 0000h

        jmp Start

        org 000bh

        jmp Timer0_Isr

        org001bh

        jmp Timer_Isr //TH0 is now occupying timer 1

        org 0030h

start:

        mov r0,#0x7f

ClrRam: //Clear internal 256Byte RAM

        mov @r0,#0

        djnz r0,ClrRam    

        mov dptr,#0x00 //Clear external 768Byte RAM

ClrOutRam:

        mov a,#0x00 //Write all 0x00 to external RAM

        movx @dptr,a

        inc dpl

        mov a,dpl

        cjne a,#0,ClrOutRam

        inc dph

        mov a,dph

        cjne a,#3,ClrOutRam 

SetTimer0:                                         

        mov tmod,#03h //Timer 1 works in mode 1

        mov th0,#HIGH(256-100)

        mov tl0,#LOW(256-100)

        setb tr0 //Start timer 0 counting

        setb et0 //Enable timer 1 interrupt

        setb tr1 //Start timer 1 counting

        setb et1 //Enable timer 1 interrupt

        setbea

main:    

        ljmp main

Timer0_Isr:

    push acc

    push psw

    mov tl0,#LOW(256-100)

    nop

    nop

    pop psw

    pop acc

    reti

Timer_Isr:

    push acc

    push psw

    mov th0,#LOW(256-100)

    nop

    nop

    pop psw

    pop acc

    reti

    end