ARM2440 LCD Experiment

1. S3C2440 internal LCD controller structure diagram:

Let's describe the LCD controller integrated in the S3C2440 according to the data sheet:

a: LCD controller consists of REGBANK, LCDCDMA, TIMEGEN, and VIDPRCS registers;

b: REGBANK consists of 17 programmable registers and a 256*16 palette memory, which are used to configure the LCD controller;

c: LCDCDMA is a dedicated DMA that can automatically transfer video data in the memory to the LCD driver. By using this DMA channel, the video data is displayed on the LCD screen without the intervention of the CPU;

d: VIDPRCS receives data from LCDCDMA, converts the data into a suitable data format, such as 4/8-bit single-scan, 4-bit double-scan display mode, and then transmits the video data to the LCD driver through the data port VD[23:0];

e: TIMEGEN is composed of programmable logic. It generates the control signals required by the LCD driver, such as VSYNC, HSYNC, VCLK and LEND. These control signals are closely related to the configuration of LCDCON1/2/3/4/5 in the REGBANK register group. Through different configurations, TIMEGEN can generate different forms of these signals to support different LCD drivers (that is, different STN/TFT screens).

The FIFO memory is located in the LCDCDMA. When the FIFO is empty or partially empty, the LCDCDMA requests to fetch the image data to be displayed from the frame buffer, which is a buffer area opened by the LCD controller in the RAM. When this transfer request is received by the bus arbitrator in the memory controller, 4 bytes will be successfully transferred from the system memory to the internal FIFO. The total size of the FIFO is 28 words, of which the low-order FIFOL is 12 words and the high-order FIFOH is 16 words.

2. Common TFT screen working timing analysis:

3.External interface signals provided by LCD:
VSYNC/VFRAME/STV: vertical synchronization signal (TFT)/frame synchronization signal (STN)/SEC TFT signal;
HSYNC/VLINE/CPV: horizontal synchronization signal (TFT)/line synchronization pulse signal (STN)/SEC TFT signal;
VCLK/LCD_HCLK: pixel clock signal (TFT/STN)/SEC TFT signal;
VD[23:0]: LCD pixel data output port (TFT/STN/SEC TFT);
VDEN/VM/TP: data enable signal (TFT)/LCD drive AC bias signal (STN)/SEC TFT signal;
LEND/STH: line end signal (TFT)/SEC TFT signal;
LCD_LPCOE: SEC TFT OE signal;
LCD_LPCREV: SEC TFT REV signal;
LCD_LPCREVB: SEC TFT REVB signal.

The principle of displaying images on all monitors is from top to bottom and from left to right. What does this mean? Let's put it this way. An image can be regarded as a rectangle, which is composed of many neatly arranged dots in rows. These dots are called pixels. Then the display principle of this image on the LCD is:
A: The display pointer starts from the first dot of the first row in the upper left corner of the rectangle, and is displayed on the LCD one dot at a time. The time line in the timing diagram above is VCLK, which we call the pixel clock signal;
B: When the display pointer is displayed all the way to the right side of the rectangle, the row ends. The action of this row in the timing diagram above is called 1 Line;
C: Then the display pointer returns to the left side of the rectangle and starts to display from the second row. Note that it takes a certain amount of time for the display pointer to return from the right side of the first row to the left side of the second row. We call it row switching;
D: And so on. The display pointer is displayed row by row to the lower right corner of the rectangle to complete the display of an image. Therefore, the display of these lines on the timeline is HSYNC on the timing diagram;
E: However, the LCD display is not a quick display of an image. In order to display it continuously and stably on the LCD, it is necessary to switch to another image (the other image can be the same or different from the previous image, the purpose is just to display the image continuously on the LCD). Then these images are called frames, which are represented as 1 Frame on the timing diagram. Therefore, it can be seen from the timing diagram that 1 Line is just a line in 1 Frame;
F: Similarly, it takes a certain amount of time to switch between frames, which we call frame switching. Then the entire LCD display process can be represented as VSYNC on the timing diagram when viewed on the timeline.

The meaning of each clock delay parameter in the timing diagram above is as follows: (The LCD manufacturer will provide the corresponding data sheet for the values ​​of these parameters)
VBPD (vertical back porch): indicates the number of invalid rows after the vertical sync signal at the beginning of a frame of image, corresponding to the upper_margin in the driver;
VFBD (vertical front porch): indicates the number of invalid rows before the vertical sync signal after the end of a frame of image, corresponding to the lower_margin in the driver;
VSPW (vertical sync pulse width): indicates the width of the vertical sync pulse, calculated by the number of rows, corresponding to the vsync_len in the driver;
HBPD (horizontal back porch): indicates the number of VCLKs from the start of the horizontal sync signal to the start of valid data of a row, corresponding to the left_margin in the driver; HFPD (horizontal front porth): indicates the number of VCLKs from the end of valid data of a row to the start of the next horizontal sync signal, corresponding to the right_margin in the driver; HSPW (horizontal sync pulse
width): indicates the width of the vertical sync pulse, calculated by the number of rows, corresponding to the vsync_len in the driver;
width): indicates the width of the horizontal synchronization signal, calculated using VCLK, corresponding to hsync_len in the driver;

Note: For an LCD screen of known size, as long as the VCLK value is determined, the horizontal frequency and field frequency should be known. But this is not enough, because in each frame clock signal, there will be some clocks that are not related to the screen display, which brings certain complexity to the determination of the horizontal frequency and field frequency. For example, in the HSYNC signal, the horizontal synchronization signal front shoulder (HFPD) and the horizontal synchronization signal back shoulder (HBPD) will appear successively, and in the VSYNC signal, the vertical synchronization signal front shoulder (VFPD) and the vertical synchronization signal back shoulder (VBPD) will appear successively. In these signal timings, there will be no valid pixel signals. In addition, when the HSYNC and VSYNC signals are valid, their levels must be maintained for a certain period of time. They are called the horizontal synchronization signal pulse width HSPW and the vertical synchronization signal pulse width VSPW respectively. There can be no pixel signals during this period. Therefore, when calculating the horizontal frequency and field frequency, these signals must be included.

The values ​​of the above parameters will be saved in the LCDCON1/2/3/4/5 registers in the REGBANK register group respectively: (For the operation of the registers, please refer to the LCD section of the S3c2440 data sheet)

4. Frame Buffer:
Frame Buffer is an interface provided by Linux for display devices. It describes some display devices as a buffer, allowing applications to access these graphics devices through the interface defined by Frame Buffer, without having to worry about the specific hardware details. For frame buffer devices, as long as the color value is written to the area corresponding to the display point in the display buffer, the corresponding color will be automatically displayed on the screen. Let's take a look at the corresponding relationship between the buffer and the display point in different color bit modes:

1. Initialization (GPC pins are used for VD[7:0], LCDVF[2:0], VM, VFRAME, VLINE, VCLK, LEND)

2. For controlling TFT LCD, you only need to set registers LCDCON1~LCDCON5 (used to select LCD type, set the time characteristics of various control signals, etc.) and LCDSADDR1~LCDSADDR3 (used to set the frame memory address).

Among them, the parameters VBPD, VFPD, VSPW, HBPD, HFPD, and HSPW are provided by LCD manufacturers and can be modified according to their datashet.

8-bit color display initializes the palette more than 16-bit

lcddrv.h

  1 /*

  2  * FILE: lcddrv.h

  3 * Low-level function interface for operating LCD controller, palette, etc.

  4  */

  5 

  6 #ifndef __LCDDRV_H__

  7 #define __LCDDRV_H__

  8 

  9 #include

 10 

 11 #define LOWER21BITS(n)  ((n) & 0x1fffff)

 12 

 13 #define BPPMODE_1BPP    0x8

 14 #define BPPMODE_2BPP    0x9

 15 #define BPPMODE_4BPP    0xA

 16 #define BPPMODE_8BPP    0xB

 17 #define BPPMODE_16BPP   0xC

 18 #define BPPMODE_24BPP   0xD

 19 

 20 #define LCDTYPE_TFT     0x3

 21 

 22 #define ENVID_DISABLE   0

 23 #define ENVID_ENABLE    1

 24 

 25 #define FORMAT8BPP_5551 0

 26 #define FORMAT8BPP_565  1

 27 

 28 #define HSYNC_NORM      0

 29 #define HSYNC_INV       1

 30 

 31 #define VSYNC_NORM      0

 32 #define VSYNC_INV       1

 33 

 34 #define BSWP            1

 35 #define HWSWP           1

 36 

 37 //TFT LCD Panel(240*320)

 38 #define MODE_TFT_1BIT_240320     (0x4101)

 39 #define MODE_TFT_8BIT_240320      (0x4102)

 40 #define MODE_TFT_16BIT_240320    (0x4104)

 41 #define MODE_TFT_24BIT_240320    (0x4108)

 42 

 43 //TFT 240320

 44 #define LCD_XSIZE_TFT_240320     (240)    

 45 #define LCD_YSIZE_TFT_240320     (320)

 46 

 47 //TFT 240320

 48 #define HOZVAL_TFT_240320    (LCD_XSIZE_TFT_240320-1)

 49 #define LINEVAL_TFT_240320    (LCD_YSIZE_TFT_240320-1)

 50 

 51 #define CLKVAL_TFT_240320    (4)

 52 // 60hz @133Mhz

 53 // (9) 60hz @100Mhz

 54 

 55 //Timing parameter for LTS350Q1(SAMSUNG) 

 56 #define VBPD_240320        ((6-1)&0xff)

 57 #define VFPD_240320        ((4-1)&0xff)

 58 #define VSPW_240320        ((2-1) &0x3f)

 59 #define HBPD_240320        ((11-1)&0x7f)

 60 #define HFPD_240320        ((2-1)&0xff)

 61 #define HSPW_240320        ((1-1)&0xff)

 62 

 63 

 64