ARM assembly instruction set 3

Common ARM instructions 1: data processing instructions

•Data transfer instructions mov mvn

      mov r1, r0 @Data transfer between two registers

      mov r1, #0xff @Assign the immediate value to the register

mov and mvn are used in the same way, the difference is that mov is passed intact, while mvn is passed after bitwise inversion

•Arithmetic instructions add sub rsb adc sbc rsc 

     and logical AND

     orr logical OR

     eor logical exclusive or

•Logical instructions and orr eor bic

    bic bit cleared

    bic r0,r1,#0x1f @clear bits 0 to 4 of r1 and assign them to r0

•Comparison instructions cmp cmn tst teq (Comparison instructions focus on the process and not the result)

   cmp r0, r1 @ equivalent to sub r2, r0,r1 (r2 = r0-r1)

   cmn r0, r1 @ is equivalent to add r0,r1

   tst r0,#0x08 @test whether bit_3 is 0

   bne suspendup @Whether the previous instruction is true or not, if true, jump to the label suspendup

   tst r0,#0x0f @test whether bits 0-3 of r0 are all 0

•Multiplication instructions mvl mla umull umlal smull smlal

• Leading zero count clz

Comparison instructions are used to compare the values ​​in two registers.
Note: comparison instructions do not need to be followed by an suffix of 's' to affect the flag bits in cpsr.

Common ARM instructions 2: cpsr access instructions: mrs & msr

•mrs is used to read psr (including cpsr, spsr), msr is used to write psrpsr (including cpsr, spsr)

      The difference and connection between cpsr and spsr: there is only one cpsr program status register in the entire SOC; while there are 5 spsrs, which are used in 5 exception modes respectively. Their function is to enter the exception mode when the normal mode enters the exception mode.

      Used to save the cpsr in the previous normal mode and restore the original spsr when returning to normal mode.

•CPSR registers are special and require special instructions to access them, namely mrs and msr.

Common ARM instructions 3: Jump (branch) instructions: b & bl & bx

•b Jump directly (if not opened, it will be considered a return)

•bl branch and link, put the return address into lr before jumping, so that it can be returned and used for function calls

•The bx jump switches to ARM mode at the same time, and is generally used for exception handling jumps.

Common ARM instructions 4: memory access instructions: ldr/str & ldm/stm & swp

• Single word/half word/byte access ldr/str

•Multi-word batch access ldm/stm

•swp r1, r2, [r0]

•swp r1, r1, [r0] (swap data between memory and register)

Immediate values ​​in ARM assembly (legal and illegal immediate values)

•ARM instructions are all 32-bit, and in addition to the instruction tag and operation tag, they can only be accompanied by a small number of immediate values. Therefore, there are legal and illegal immediate values.

• Legal immediate number: After any number of shifts, the non-zero part can be represented by 8 bits, which is a legal immediate number.

  For example: Legal immediate number: 0x000000ff, 0x00ff0000

       Illegal immediate value: 0x000001ff

Common ARM instructions 5: software interrupt instruction: swi (software interrupt)

•Soft interrupt instructions are used to implement system calls in the operating system