arm assembly syntax

    area abc123, code, readonly;

    entry 

    code32

start

    mov r1, #5

    mov r2, #2

    add r0, r1, r2

    end

I installed ADS 1.2; I am a novice and I don't know how to use it. I am not used to it.

It's terrible, there is no keyword syntax highlighting! The above code compiles successfully, except for the instructions such as mov and add, which can be distinguished immediately, who can think of what area is used for?

If I change abc123 to asm, will other newcomers mistakenly think that asm is a keyword?

The problem is that the first three lines and the last line "end" must start with a tab character, which is very annoying for the makefile. I encountered another syntax rule like this;

When programmers learn something, they always have to spend a considerable amount of time getting familiar with the weird and incomprehensible syntax!!!

-------------- When I master a unique skill and unify the syntax of all programming languages, any programmer only needs to learn one universal syntax and can program everywhere;

In fact, ARM assembly should be very simple, 37 registers, 53 instruction mnemonics; that's it...

　　ARM instruction set: 6 types (53 main mnemonics):

　　　　1. Data processing instructions (22 main mnemonics)

　　　　2. Jump instructions (4 main mnemonics)

　　　　3. Load/Store instructions (16 main mnemonics)

　　　　4. Program Status Register Instructions (2 main mnemonics)

　　　　5. Coprocessor instructions (5 main mnemonics)

　　　　6. Software interrupt instructions (2 main mnemonics)

The registers available in 32-bit mode on ARM 6 (and later) are: 

User26 SVC26 IRQ26 FIQ26 User SVC IRQ ABT UND FIQ

R0 ----- R0 ----- R0 ----- R0 -- -- R0 ----- R0 ----- R0 ----- R0 ----- R0 ----- R1

R1 ----- R1 ----- R1 ----- R1 -- -- R1 ----- R1 ----- R1 ----- R1 ----- R1 ----- R2

R2 ----- R2 ----- R2 ----- R2 -- -- R2 ----- R2 ----- R2 ----- R2 ----- R2 ----- R2

R3 ----- R3 ----- R3 ----- R3 -- -- R3 ----- R3 ----- R3 ----- R3 ----- R3 ----- R3

R4 ----- R4 ----- R4 ----- R4 -- -- R4 ----- R4 ----- R4 ----- R4 ----- R4 ----- R4

R5 ----- R5 ----- R5 ----- R5 -- -- R5 ----- R5 ----- R5 ----- R5 ----- R5 ----- R5

R6 ----- R6 ----- R6 ----- R6 -- -- R6 ----- R6 ----- R6 ----- R6 ----- R6 ----- R6

R7 ----- R7 ----- R7 ----- R7 -- -- R7 ----- R7 ----- R7 ----- R7 ----- R7 ----- R7

R8 ----- R8 ----- R8 R8_fiq R8 ----- R8 ----- R8 ----- R8 ----- R8 R8_fiq

R9 ----- R9 ----- R9 R9_fiq R9 ----- R9 ----- R9 ----- R9 ----- R9 R9_fiq

R10 ---- R10 ---- R10 R10_fiq R10 ---- R10 ---- R10 ---- R10 ---- R10 R10_fiq

R11 ---- R11 ---- R11 R11_fiq R11 ---- R11 ---- R11 ---- R11 ---- R11 R11_fiq

R12 ---- R12 ---- R12 R12_fiq R12 ---- R12 ---- R12 ---- R12 ---- R12 R12_fiq

R13 R13_svc R13_irq R13_fiq R13 R13_svc R13_irq R13_abt R13_und R13_fiq

R14 R14_svc R14_irq R14_fiq R14 R14_svc R14_irq R14_abt R14_und R14_fiq

--------- R15 (PC / PSR) --------- --------------------- R15 (PC) ---------------------

----------------------- CPSR -----------------------

SPSR_svc SPSR_irq SPSR_abt SPSR_und SPSR_fiq

ADC Addition with Carry -  

ADD Addition -  

AND Logical AND -  

ASL Arithmetic Shift Left This is an option, not an instruction.  

ASR Arithmetic Shift Right This is an option, not an instruction.  

B Branch -  

BIC bit clear -  

BL Branch with connection -  

BX branch to Thumb code StrongARM SA1110 ? 

CDP Coprocessor Data Operations -  

CMN compares the negative value -  

CMP Comparison Value -  

EOR Exclusive OR of two values ​​-  

LDC Load memory to coprocessor -  

LDM Load Multiple Registers -  

LDR Load Register -  

LDRB Load byte into register -  

LDRH Load halfword into register StrongARM 

LDRSB Load signed byte into register StrongARM  

LDRSH Load signed halfword into register StrongARM   

LSL Logical Shift Left This is an option, not an instruction. 

LSR Logical Shift Right This is an option, not an instruction. 

MCR Coprocessor Register Transfer - 

MLA Multiplication with Accumulation -  

MOV moves a value/register to a register -  

MRC Coprocessor Register Transfer -  

MRS transfer status flags to a register ARM 6  

MSR transfers the contents of a register to the status flags ARM 6  

MUL Multiplication -  

MVN Transmits a negative value -  

ORR Logical OR -  

ROR Rotate Right This is an option, not an instruction.   

RRX Rotate Right with Extend This is an option, not an instruction.   

RSB Reverse Subtraction -   

RSC Reverse subtraction with borrow -   

SBC Subtraction with Borrow -   

SMLAL Signed long (64-bit) multiply with accumulate StrongARM   

SMULL Signed long (64-bit) multiplication StrongARM   

STC Coprocessor Data Transfer -   

STM stores multiple registers -   

STR stores a register -   

STRB stores a byte (from a register) -   

STRH Store a halfword (from a register) StrongARM   

STRSB Store a signed byte (from a register) StrongARM   

STRSH Store a signed halfword (from a register) StrongARM   

SUB Subtraction -   

SWI causes a software interrupt -   

SWP Swap Register with Memory ARM 3   

TEQ Test Equivalence (Conceptual EOR) -   

TST Test and Screen (conceptual AND) -   

UMLAL Unsigned long (64-bit) multiply with accumulate StrongARM   

UMULL Unsigned long (64-bit) multiplication StrongARM