ARM——I2C

　　The S5PC100's RISC microprocessor supports a multi-master I2C bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) pass information between the bus master and the peripheral devices connected to the I2C bus. The SDA and SCL lines are bidirectional.

　　In multi-master I2C bus mode, multiple microprocessors send to and receive from slave devices. The master S5PC100 initiates and terminates a data transfer on the I2C bus. The I2C bus on the S5PC100 uses the standard bus arbitration procedure.

　　To control multi-master I2C bus operation, values ​​must be written to the following registers:

　　Multi-master I2C control register I2CCON

　　Multi-master I2C control/status register I2CSTAT

　　Multi-master I2C send/receive conversion register I2CDS

　　Multi-master I2C address register I2CADD

　　If the I2C bus is idle, both the SDA and SCL lines should be high. When the SCL line is stable at a high level, a high-to-low transition on the SDA line will initiate a start condition, and a low-to-high transition on the SDA line will initiate a stop condition.

　　The master device always generates the start and stop conditions. When the start condition is issued, the 7-bit address value of the first data byte placed on the bus can determine the slave device selected by the bus master device. The 8th bit determines the transfer direction (read/write).

　　Each data byte placed on the SDA line should be a total of eight bits. There is no limit to the number of data bytes sent or received during a bus transfer. Data is always sent with the most significant bit, MSB, first, followed by an acknowledge bit, ACK, after each byte.

　　The S5PC100 I2C bus interface has four operating modes:

　　Master send mode; Master receive mode; Slave send mode; Slave receive mode

These operating modes function in the following ways:

Start and Stop Conditions

　　If the I2C bus interface is not started, it is usually in slave mode. In other words, the interface should be in slave mode before detecting the start condition on the SDA line (the SDA line level changes from high to low when the SCL line clock signal is high). If the interface state changes to master mode, data transmission on the SDA line can be initiated and the SCL signal is generated.

　　The start condition of the SDA line transmits one byte of serial data, and the stop condition terminates the data transmission. When the SCL line clock signal is high, the SDA line level changes from low to high to initiate the stop condition. The master generates start and stop conditions. If the start condition is generated, the I2C bus will become busy. The stop condition releases the I2C bus. If the master initiates the start condition, a slave address should be sent to notify the slave device. The one-byte address field contains a 7-bit address value and a 1-bit transmission direction indication value (write or read). If the 8th bit is 0, it indicates a write operation (send operation); if the 8th bit is 1, it indicates a read data request (receive operation).

　　The host sends a stop condition to complete the transfer operation. If the host box continues to send bus data, it should generate another start condition and slave address. In this way, various formats of read and write operations can be performed.

Data transmission format 

Each byte on the SDA line should be 8 bits long. There is no limit to the number of bytes sent per transfer. The first byte following the start condition should contain the address field. If the I2C bus operates in master mode, the master sends the address field. Each byte should be followed by an acknowledge bit ACK. The most significant bit of the serial data and address should be sent first.

Reply signal sent

To complete a byte transfer operation, the receiver sends an ACK to the sender. The ACK pulse is generated at the 9th clock cycle of the SCL line. Eight clocks are used for a byte of data transfer. The host generates a clock pulse when sending the ACK.

If the transmitter receives the ACK bit, it releases the SDA line by setting the SDA line high. The receiver drives the SDA line low during the ACK clock pulse to keep the SDA line low during the 9th pulse cycle of the SCL line.

Software (I2CSTAT) enables or disables the ACK bit transmission function. However, the ACK bit pulse is requested in the 9th pulse cycle of the SCL line to complete a byte data transfer operation.

 Read/Write Operations

In the sending mode, if data is transmitted, the I2C bus interface waits until the I2C bus data transfer register (I2CDS) receives a new data. Before the new data is written to the register, the SCL line remains at a low level, and then released after writing. S5PC100 gets an interrupt to identify whether the current data transmission is completed. After the CPU receives the interrupt request, it writes a new data to the I2CDS register.

In receive mode, if data is received, the I2C bus interface waits until the I2C bus data transfer register (I2CDS) is read. Before the new data is read, the SCL line remains low and then released after reading. The S5PC100 gets an interrupt to identify whether the current data reception is completed. After the CPU receives the interrupt request, it reads data from the I2CDS register.

Bus arbitration procedure

Arbitration occurs on the SDA line to prevent conflicts between two masters on the bus. If a master with a high SDA line detects another master with a low SDA line, it will not initiate data transmission because the current level on the bus cannot correspond to itself. The arbitration procedure is delayed until the SDA line level becomes high.

If the masters simultaneously lower the SDA line level, each master evaluates whether it is the master right. To evaluate each master, the address bit is detected. When each master generates a slave address, the address bit on the SDA line is detected because the SDA line is more likely to obtain a low level than to remain at a high level. Suppose one master generates a low level as the first bit of the address and the other maintains a high level. In this case, both masters detect a low level on the bus because the low level state is superior to the high level state. If this happens, the master that generates a low level (as the first bit of the address) obtains the master right and the master that generates a high level (as the first bit of the address) withdraws the master right. If the master generates a low level as the first bit of the address, arbitration is performed on the second address bit. This arbitration continues until the address bit ends.

Cancellation conditions

If the slave receiver fails to acknowledge the slave address, it will keep the SDA line high. In this case, the master generates a stop condition and terminates the transfer.

If the master receiver is busy with the aborted transfer, it signals the abort of the slave transmission by deasserting the acknowledge bit ACK after the slave has received the last data byte. The slave transmitter releases the SDA line to allow the master to generate a stop condition.

Configuring the I2C Bus

To control the frequency of the serial bus clock SCL, a 4-bit prescaler value is written to the I2CCON register. The I2C-bus interface address is stored in the I2C-bus address (I2CADD) register (by default the I2C-bus interface address has an unknown value).

Operation flow chart for each mode

The following steps are performed in every I2C transmit/receive operation

1 If necessary, own slave address to I2CADD register

2Set up the I2CCON register

　　a Enable interrupt

　　b defines the SCL cycle

3 Set I2CSTAT to enable serial port output

#include "s5pc100.h"

void putc(const char data)
{
 while(!(UART0.UTRSTAT0 & 0X2));
 UART0.UTXH0 = data;
 if(data == 'n')
  putc('r');
}
void puts(const  char  *pstr)
{
 while(*pstr != '')
  putc(*pstr++);
}

void uart0_init(void)
{
 GPA0.GPA0CON = (GPA0.GPA0CON & ~(0xff)) | 0X22;//enable GPA0.0 GPA0.1 pin function mode // RXD0 TXD0
    UART0.UFCON0 = 0X00; //disable  fifo
 UART0.UMCON0 = 0X00; //disable AFC
 UART0.ULCON0 = 0X03; //data length 8 bit
 UART0.UCON0  = 0X305; //
 UART0.UBRDIV0 = 0X23; // Baud rate divisior register 115200   UBRDIV0 = (PCLK / (bps x 16 ) ) 
 UART0.UDIVSLOT0 = 0xDDD5;   //set  SLOT  register  generate more accurate baud rate
    printf("open uart device ok !n");
}

 #include "s5pc100.h"
#include "uart.h"

/****
 * functioal : Reading the value of the internal lm75 register
 * param:  address register of the internal lm75 register
 * return: value of the internal lm75 register
 */
int set_pointer_and_read_temperature(void)
{ 

 int delay;
 int low, high;
 I2C0.I2CDS0 = 0x90;       /*LM75 SLAVE ADDRESS */
 I2C0.I2CCON0 = 0xe0;       /*ENABLE ACK BIT, PRESCALER:512 ,RX/TX INTERRUPT ENABLE ,*/
 I2C0.I2CSTAT0 =0xf0;       /*Master Trans mode ,START ,ENABLE RX/TX ,*/
 while(!(I2C0.I2CCON0&(1<<4)));  /*The end of the waiting to be sent  */
 
 I2C0.I2CDS0 = 0x0;        /*pointer register Temperature(read only) send address of SFR in the lm75*/
 I2C0.I2CCON0 &= ~(1<<4);        /* Clear pending condition & Resume the operation */
 while(!(I2C0.I2CCON0&(1<<4)));  /*The end of the waiting to be sent  */
 
 I2C0.I2CDS0 = 0x90;            /*Again to send LM75 salve address*/
 I2C0.I2CSTAT0 =0xb0;     /*Master receive mode ,START ,ENABLE RX/TX ,*/
 I2C0.I2CCON0  &= ~(1<<4);    /* Clear pending condition & Resume the operation */
 while(!(I2C0.I2CCON0&(1<<4))); /*The end of the waiting to be sent  */

 I2C0.I2CCON0 &= ~(1<<4);        /* Clear pending condition & Resume the operation */
 for(delay=0; delay<0xffff; delay++);
 high = I2C0.I2CDS0;             /*read temperature of high 8 bit */

 I2C0.I2CCON0 &= ~(1<<4);       /* Clear pending condition & Resume the operation */
 for(delay=0; delay<0xffff; delay++); 
 low = I2C0.I2CDS0;    /*read temperature of low 1 bit */

 I2C0.I2CSTAT0 &= ~(1<<5);   /*STOP signal generation,free bus */
 I2C0.I2CCON0 &= ~(1<<4);  /*clean interrup pending bit  */
 return ((high << 8) | low);
}