I2C Protocol---I2C Timing Diagram Analysis

1. Introduction to I2C Protocol

  The I2C communication protocol (Inter-Integrated Circuit) was developed by Phiilps. It has few pins, simple hardware implementation, strong scalability, and does not require external transceiver devices such as USART and CAN communication protocols. It is now widely used for communication between multiple integrated circuits (ICs) in the system. 
  For more information about the I2C protocol, you can read "I2C Bus Protocol". This blog post mainly analyzes the I2C waveform diagram, and does not introduce the basic knowledge of I2C.

https://www.cnblogs.com/Tangledice/p/7622794.html

 

5. Additional

5.1 Data Validity

        When the I2C bus is transmitting data, the data on the data line must remain stable while the clock signal is at a high level. The high or low level state of the data line is allowed to change only when the signal on the clock line is at a low level.

       However, although it is only required to remain stable during the high level period, there must be an advance amount, that is, the data is ready before the rising edge of SCL arrives, because the data is entered into the device EEPROM on the rising edge of SCL.

5.2 Data Transmission

        Each bit of data transmitted on the I2C bus has a corresponding clock pulse, that is, with the cooperation of the SCL serial clock, each bit of data is transmitted serially on SDA bit by bit. The data transmission is edge triggered.

5.3 Working process

        All communications on the bus are initiated by the master.

        1. The master device sends data to the slave device

         After the master device addresses the slave device, it sends the internal register address of the slave device to be read or written (the register address is set by itself and is used to store the storage location of the written or read data); then, it sends the data. After the data is sent, it sends the stop bit.

         After receiving the stop signal, the EEPROM enters an internal write cycle, which takes about 10ms. During this period, any operation will not be responded to by the EEPROM (a delay must be inserted between two writes in this way, otherwise it will fail).

5.4 Additional

     1) The maximum length of IIC wiring is 40CM;