How does ARM implement absolute address jump?

Analysis based on b jump instruction, ldr pseudo instruction, ldr load instruction

The following scenarios require

1. After executing some instructions from Stepingstone, you need to jump to SDRAM for execution. The prerequisite is that you must first copy the code in NAND FLASH to SDRAM before you can jump to SDRAM for execution. To jump to SDRAM, you need to use the LDR pseudo instruction LDR PC,=SDRAM to implement

analyze:

The b instruction is a relative jump instruction. You can see that the disassembled code is exactly the same. It depends on the value of the current PC register. Regardless of the link address of this code, the b instruction can jump to the correct position. This type of instruction is called a position-independent instruction.

ldr pc,=labr pseudo-instruction. As can be seen from the disassembled code, it reads data from a certain location in the memory and assigns it to the pc register. The value stored in it depends on the link address of the link script file. It is an absolute jump instruction.

2. To debug interrupts in SDRAM, the interrupt vector must also be placed at 0x00000000 to jump to the corresponding position in SDRAM

Vectors         

ldr PC, Reset_Addr ;@0x00 reset    

ldr PC, Undef_Addr ;@ 0x04: vector address of undefined instruction abort mode

ldr PC, SWI_Addr ;@ 0x08: vector address of management mode, enter this mode through SWI instruction

ldr PC, PAbt_Addr ;@ 0x0c: vector address of exception caused by instruction prefetch termination

ldr PC, DAbt_Addr ;@ 0x10: vector address of the exception caused by data access termination

nop ;@ 0x14: reserved

ldr PC, IRQ_Addr ;@ 0x18: interrupt mode vector address

ldr PC, FIQ_Addr ;@ 0x1c: vector address of fast interrupt mode

Reset_Addr      DCD     Reset_Handler

Undef_Addr      DCD     Undef_Handler

SWI_Addr        DCD     SWI_Handler

PAbt_Addr       DCD     PAbt_Handler

DAbt_Addr DCD DAbt_Handler

                nop

IRQ_Addr        DCD     IRQ_Handler

FIQ_Addr DCD FIQ_Handler

Reset_Handler                

Undef_Handler b Undef_Handler ; not used, can be reserved with this instruction

SWI_Handler b SWI_Handler ; not used, can be reserved with this instruction

PAbt_Handler b PAbt_Handler ; not used, can be reserved with this instruction

DAbt_Handler b DAbt_Handler ;Not used, can be reserved with this instruction

FIQ_Handler b FIQ_Handler ; not used, can be reserved with this instruction

IRQ_Handler

    sub lr, lr, #4 ;@ Calculate the return address

    stmdb sp!, { r0-r12,lr } ;@ Save the used registers

                                    ;@ Note that the sp at this time is the sp in interrupt mode

                                     ;@ The initial value is 3072 set above

ldr lr , =int_return

    ldr pc, =EINT_Handle ;@ Call interrupt service function in interrupt.c

int_return; Because the ldr jump cannot save the address of the next instruction to lr, it is necessary to save the instruction before the jump.

    ldmia sp!, { r0-r12,pc }^ ;@ interrupt return, ^ means copy the value of spsr to cpsr

    END

Use the ldr load instruction (not the ldr pseudo-instruction) to implement absolute address jump

The hander label depends on the setting of the link script address. The hander address is placed in the memory labeled step3, so as to achieve the purpose of absolute address jump.

+++++++++++link2.s+++++++++

.text

.global _start

_start:         b   step1

step1:          ldr pc,=step2

step2:          ldr pc,step3

step3:          .long   hander

hander:         b step4

step4:          b step4

+++++++++++Makefile++++++++++++++

link2:  link2.s

arm-linux-gcc -c -o link2.o link2.s

arm-linux-ld -Ttext 0x00000000 link2.o -o link2_elf_0x00000000

arm-linux-ld -Ttext 0x30000000 link2.o -o link2_elf_0x30000000

arm-linux-objdump -D link2_elf_0x00000000 > link2_0x00000000_dis

arm-linux-objdump -D link2_elf_0x30000000 > link2_0x30000000_dis

clean :

rm -f  *.o

link2_elf_0x30000000:    file format elf32-littlearm

Disassembly of section .text:

30000000

30000000:  eaffffff      b       30000004

30000004

30000004:  e59ff00c   ldr     pc, [pc, #12]; 30000018

30000008

30000008:  e51ff004   ldr     pc, [pc, #-4]         ; 3000000c

3000000c

3000000c:  30000010 .word         0x30000010

30000010

30000010:  eaffffff      b       30000014

30000014

30000014:  eafffffe     b       30000014

30000018:  30000008 .word         0x30000008

link2_elf_0x00000000:    file format elf32-littlearm

Disassembly of section .text:

00000000

   0:          eaffffff      b       4

00000004

   4:          e59ff00c   ldr     pc, [pc, #12]        ; 18

00000008

   8:          e51ff004   ldr     pc, [pc, #-4]         ; c

0000000c

   c: 00000010 .word         0x00000010

00000010

  10:          eaffffff      b       14

00000014

  14:          eafffffe     b       14

  18:          00000008 .word         0x00000008