【stm32f407】NVIC

NVIC is called "Nested Vectored Interrupt Controller (NVIC)".

The CM4 core supports 256 interrupts, including 16 core interrupts and 240 external interrupts, and has 256 levels of programmable interrupt settings. However, the STM32F4 does not use all of the CM4 core, but only uses part of it.

STM32F40xx/STM32F41xx has a total of 92 interrupts, and STM32F42xx/STM32F43xx has a total of 96 interrupts. The following only takes STM32F40xx/41xx as an example.

Among the 92 interrupts of STM32F40xx/STM32F41xx, there are 10 core interrupts and 82 maskable interrupts, with 16 levels of programmable interrupt priority. We often use these 82 maskable interrupts. In MDK, the registers related to NVIC have the following structure defined by MDK:

typedefstruct

{

__IOuint32_t ISER[8];   /*!< Interrupt SetEnable Register */

uint32_tRESERVED0[24];

__IOuint32_t ICER[8];      /*!< InterruptClear Enable Register */

uint32_tRSERVED1[24];

__IOuint32_t ISPR[8];      /*!< InterruptSet Pending Register */

uint32_tRESERVED2[24];

__IOuint32_t ICPR[8];      /*!< InterruptClear Pending Register */

uint32_tRESERVED3[24];

__IOuint32_t IABR[8];        /*!

uint32_tRESERVED4[56];

__IOuint8_t IP[240];    /*!< InterruptPriority Register, 8Bit wide      */

uint32_tRESERVED5[644];

__Ouint32_t STIR;      /*!< SoftwareTrigger Interrupt Register */

}NVIC_Type;

The interrupts of STM32F4 are executed in order under the control of these registers. Only by understanding these interrupt registers can we conveniently use the interrupts of STM32F4. The following focuses on these registers:

ISER[8]: ISER stands for Interrupt Set-Enable Registers, which is an interrupt enable register group. As mentioned above, the CM4 core supports 256 interrupts, which are controlled by 8 32-bit registers, each of which controls one interrupt. However, the STM32F4 has a maximum of 82 maskable interrupts, so for us, there are only three (ISER[0~2]), which can represent a total of 96 interrupts. However, the STM32F4 only uses the first 82 of them. Bits 0~31 of ISER[0] correspond to interrupts 0~31; bits 0~32 of ISER[1] correspond to interrupts 32~63; bits 0~17 of ISER[2] correspond to interrupts 64~81; thus, a total of 82 interrupts are matched. If you want to enable an interrupt, you must set the corresponding ISER bit to 1 to enable the interrupt (this is just enabling, and it must be combined with interrupt grouping, masking, IO port mapping and other settings to be considered a complete interrupt setting).

ICER[8]: The full name is Interrupt Clear-Enable Registers, which is an interrupt disable register group. This register group has the opposite function to ISER, and is used to clear the enable of a certain interrupt. The function of its corresponding bit is the same as ICER. Here, an ICER is specially set to clear the interrupt bit, instead of writing 0 to ISER to clear it, because these registers of NVIC are valid when writing 1, and invalid when writing 0.

ISPR[8]: The full name is Interrupt Set-Pending Registers, which is an interrupt pending control register group. The interrupt corresponding to each bit is the same as ISER. By setting 1, the ongoing interrupt can be suspended and the same or higher level interrupt can be executed. Writing 0 is invalid.

ICPR[8]: The full name is Interrupt Clear-Pending Registers, which is an interrupt clear control register group. Its function is opposite to ISPR, and the corresponding bits are the same as ISER. By setting 1, the pending interrupt can be cleared. Writing 0 has no effect.

IABR[8]: The full name is Interrupt Active Bit Registers, which is an interrupt active flag register group. The interrupt represented by the corresponding bit is the same as ISER. If it is 1, it means that the interrupt corresponding to the bit is being executed. This is a read-only register, which can be used to know which interrupt is currently being executed. It is automatically cleared by hardware after the interrupt is executed.

IP[240]: The full name is: Interrupt Priority Registers, which is a register group for interrupt priority control. This register group is very important! The interrupt grouping of STM32F4 is closely related to this register group. The IP register group consists of 240 8-bit registers, and each maskable interrupt occupies 8 bits, so a total of 240 maskable interrupts can be represented. However, STM32F4 only uses 82 of them. IP[81]~IP[0] correspond to interrupts 81~0 respectively. However, the 8 bits occupied by each maskable interrupt are not all used, but only the upper 4 bits are used. These 4 bits are divided into preemption priority and response priority. The preemption priority is in front and the response priority is in the back. The number of bits occupied by each of these two priorities depends on the interrupt grouping settings in SCB->AIRCR.

Here is a brief introduction to the interrupt grouping of STM32F4: STM32F4 divides interrupts into 5 groups, group 0 to 4. The setting of this grouping is defined by bits 10 to 8 of the SCB->AIRCR register. As shown in the figure:

Through this table, we can clearly see the configuration relationship corresponding to groups 0~4. For example, if group is set to 3, then for all 82 interrupts, the highest 3 bits of the upper 4 bits of the interrupt priority register of each interrupt are the preemption priority, and the lower 1 bit is the response priority. For each interrupt, you can set the preemption priority to 0~7 and the response priority to 1 or 0. The preemption priority is higher than the response priority. The smaller the value, the higher the priority.

There are two points to note here:

First, if the preemption priority and response priority of two interrupts are the same, the interrupt that occurs first will be executed first;

Second, a high-priority preemption priority can interrupt an ongoing low-priority preemption interrupt. For interrupts with the same preemption priority, a high-priority response priority cannot interrupt a low-priority response interrupt.

Let's explain with an example: Assume that the interrupt priority group is set to 2, and then set the preemption priority of interrupt 3 (RTC_WKUP interrupt) to 2 and the response priority to 1. The preemption priority of interrupt 6 (external interrupt 0) is 3 and the response priority is 0. The preemption priority of interrupt 7 (external interrupt 1) is 2 and the response priority is 0. Then the priority order of these three interrupts is: interrupt 7> interrupt 3> interrupt 6.

In the above example, both interrupt 3 and interrupt 7 can interrupt interrupt 6. However, interrupt 7 and interrupt 3 cannot interrupt each other!

Through the above introduction, we are familiar with the general process of STM32F4 interrupt setting.

Let's take an example:

Preemption priority and response priority The interrupt vector of STM32 has two attributes, one is the preemption attribute and the other is the response attribute. The smaller the attribute number, the higher its priority.

Preemption refers to the property of interrupting other interrupts. Because of this property, nested interrupts will occur.

(The interruption is interrupted by interruption B during the execution of interruption service function A. The interruption continues after the execution of interruption service function B.

Execute interrupt service function A), the preemption attribute is determined by the parameter NVIC_IRQChannelPreemptionPriority

The response attribute is applied when the preemption attribute is the same. When the preemption priority of two interrupt vectors is

If two interrupts arrive at the same time, the interrupt with higher priority will be processed first. The response attribute is configured by the parameters of NVIC_IRQChannelSubPriority. For example, there are three interrupt vectors:

Interrupt vector Preemption priority Response priority

A  0  0

B  1  0

C  1  1

If the kernel is executing the interrupt service function of C, it can be preempted by the interrupt A with higher priority.

Since B and C have the same preemption priority, C cannot be interrupted by B. However, if B and C are interrupted

If the A and B interrupts arrive at the same time, the kernel will respond to the B interrupt with a higher priority first.

Next, we will introduce how to use library functions to implement the above interrupt grouping settings and interrupt priority management, so that our future interrupt settings are simplified. The NVIC interrupt management function is mainly in the misc.c file.

The first thing to explain is the interrupt priority grouping function NVIC_PriorityGroupConfig, whose function declaration is as follows

voidNVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);

The function of this function is to group the priority of interrupts. This function can only be called once in the system. Once the grouping is determined, it is best not to change it. We can find its implementation:

voidNVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)

{

assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));

SCB->AIRCR= AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;

}

From the function body, we can see that the only purpose of this function is to set the interrupt priority group by setting the SCB->AIRCR register, which has been mentioned in the previous register explanation. The entry parameter can be viewed by double-clicking "IS_NVIC_PRIORITY_GROUP" in the function body and then right-clicking "Go to definition of..."

This is what we mentioned above, the grouping range is 0-4. For example, if we set the interrupt priority grouping value of the entire system to 2, then the method is:

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);

This determines a total of "2-bit preemption priority and 2-bit response priority".

After setting up the system interrupt grouping, how do we determine the preemption priority and response priority for each interrupt? Next, we will explain an important function, the interrupt initialization function NVIC_Init, whose function declaration is:

voidNVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)

NVIC_InitTypeDef is a structure. Let's look at the member variables of the structure:

typedefstruct

{

uint8_tNVIC_IRQChannel; 

uint8_tNVIC_IRQChannelPreemptionPriority;

uint8_tNVIC_IRQChannelSubPriority; 

FunctionalStateNVIC_IRQChannelCmd; 

} NVIC_InitTypeDef;

There are four member variables in the middle of the NVIC_InitTypeDef structure. Next, let's take a look at the meanings of these member variables one by one.

NVIC_IRQChannel: Defines which interrupt is initialized. We can find the corresponding name of each interrupt in stm32f4xx.h. For example, USART1_IRQn. NVIC_IRQChannelPreemptionPriority: Defines the preemption priority of this interrupt. NVIC_IRQChannelSubPriority: Defines the sub-priority of this interrupt, also called response priority. NVIC_IRQChannelCmd: Whether the interrupt channel is enabled.

For example, if we want to enable the interrupt of serial port 1, set the preemption priority to 1 and the response priority to 2, the initialization method is:

NVIC_InitTypeDef  NVIC_InitStructure;;

NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; //Serial port 1 interrupt

NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1; // The preemption priority is 1

NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; // Response priority 2

NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //IRQ channel enable

NVIC_Init(&NVIC_InitStructure); //Initialize the NVIC registers according to the parameters specified above

Here we explain the concept of interrupt grouping and how to set the priority of a single interrupt. For each interrupt, there are some operations such as clearing the interrupt and checking the interrupt status. We will explain how to use them in detail later when we explain each interrupt.

Finally, let's summarize the steps of interrupt priority setting:

1. Set the interrupt group at the beginning of system operation. Determine the group number, that is, determine the number of bits allocated for preemption priority and response priority. The calling function is NVIC_PriorityGroupConfig();

2. Set the interrupt priority level of the interrupt used. The function called for each interrupt is NVIC_Init();