The difference between SPI, I2C and UART serial bus protocols

The first difference is of course the name:

     SPI (Serial Peripheral Interface);

     I2C(INTER IC BUS)

     UART (Universal Asynchronous Receiver Transmitter)

Second, the difference is in the electrical signal line:

     The SPI bus consists of three signal lines: serial clock (SCLK), serial data output (SDO), and serial data input (SDI). The SPI bus can connect multiple SPI devices to each other. The SPI device that provides the SPI serial clock is the SPI host or master device (Master), and the other devices are SPI slave devices or slave devices (Slave). Full-duplex communication can be achieved between the master and slave devices. When there are multiple slave devices, a slave device selection line can be added.

     If you use a general IO port to simulate the SPI bus, you must have an output port (SDO) and an input port (SDI). The other port depends on the type of device to be implemented. If you want to implement a master-slave device, you need an input and output port. If you only want to implement a master device, you only need an output port. If you only want to implement a slave device, you only need an input port.

     The I2C bus is a bidirectional, two-wire (SCL, SDA), serial, multi-master interface standard with a bus arbitration mechanism, which is very suitable for short-distance, infrequent data communication between devices. In its protocol system, the device address of the destination device is always included when transmitting data, so device networking can be achieved.

     If you use a general IO port to simulate the I2C bus and implement bidirectional transmission, you need an input and output port (SDA) and an output port (SCL). (Note: I don't know much about I2C, so the description here may be incomplete)

     The UART bus is an asynchronous serial port, so it is generally much more complicated than the first two synchronous serial ports. It is generally composed of a baud rate generator (the generated baud rate is equal to 16 times the transmission baud rate), a UART receiver, and a UART transmitter. The hardware consists of two wires, one for sending and one for receiving.

     Obviously, if a general IO port is used to simulate a UART bus, one input port and one output port are required.

Third, it is obvious from the second point that SPI and UART can achieve full duplex, but I2C cannot;

Fourth, take a look at the opinions of the experts!

     wudanyu: I2C has fewer lines, and I think it is more powerful than UART and SPI, but it is also more technically complicated because I2C requires the support of bidirectional IO and uses pull-up resistors. I think its anti-interference ability is weak. It is generally used for communication between chips on the same board, and is rarely used for long-distance communication. SPI is simpler to implement. UART requires a fixed baud rate, which means that the interval between two bits of data must be equal, while SPI does not matter because it is a clocked protocol.

     quickmouse: I2C is a bit slower than SPI, and the protocol is a bit more complicated than SPI, but it also has fewer wires than standard SPI.

SPI interface introduction (transfer)

These days I came across a flash using the SPI interface, and only then did I realize that flash can also be serial. It seems that I was really a frog in a well before. I looked for some information on the SPI interface but it was not complete. Later, I found some English information, translated it, and added my personal understanding to put together an article. I hope it will be of some help to beginners.

   The full name of SPI interface is "Serial Peripheral Interface", which means serial peripheral interface. It was first defined by Motorola on its MC68HCXX series processors. SPI interface is mainly used in EEPROM, FLASH, real-time clock, AD converter, and between digital signal processor and digital signal decoder.

   The SPI interface is a synchronous serial data transmission between the CPU and peripheral low-speed devices. Under the shift pulse of the master device, data is transmitted bit by bit, with the high bit first and the low bit last. It is full-duplex communication. The data transmission speed is generally faster than the I2C bus, and the speed can reach several Mbps.

   The SPI interface works in master-slave mode. This mode usually has one master device and one or more slave devices. Its interface includes the following four signals:

(1) MOSI – Master device data output, slave device data input

(2) MISO – Master data input, slave data output

(3) SCLK – clock signal, generated by the master device

(4) /SS – Slave enable signal, controlled by the master device

In point-to-point communication, the SPI interface does not require addressing operations and is full-duplex communication, making it simple and efficient.

 In a system with multiple slave devices, each slave device requires an independent enable signal, which is slightly more complicated in hardware than the I2C system.

The internal hardware of the SPI interface is actually two simple shift registers. The data transmitted is 8 bits. Under the slave enable signal and shift pulse generated by the master device, the data is transmitted bit by bit, with the high bit first and the low bit last. As shown in the figure below, the data changes on the falling edge of SCLK, and one bit of data is stored in the shift register at the same time.

 SPI interface internal hardware diagram:

 Finally, one disadvantage of the SPI interface is that there is no specified flow control and no response mechanism to confirm whether the data has been received.

SPI interface

SPI interface introduction
    SPI is a synchronous serial transmission specification introduced by Motorola, USA, and is often used as a serial expansion interface for microcontroller peripheral chips. SPI has 4 pins: SS (slave select line), SDO (serial data output line), SDI (serial data input line) and SCK (synchronous serial clock line). SPI can send and receive 8 (16) bits of data simultaneously in full-duplex communication mode. The process is as follows: the host starts the sending process, sends out a clock pulse signal, and the data in the master shift register is shifted into the slave shift register through SDO, and at the same time, the data in the slave shift register is shifted into the master shift register through SDI. After 8 (16) clock pulses, the clock pauses, and the 8 (16) bits of data in the master shift register are all shifted into the slave shift register, and then automatically loaded into the slave receive buffer, and the slave receive buffer full flag (BF) and interrupt flag (SSPIF) are set to "1". Similarly, the 8 bits of data in the slave shift register are all shifted into the master register, and then automatically loaded into the master receive buffer. The master receive buffer full flag (BF) and interrupt flag (SSPIF) are set to "1". After the master CPU detects that the master receive buffer is full or the interrupt flag is set to 1, it can read the data in the receive buffer. Similarly, after the slave CPU detects that the slave receive buffer is full or the interrupt flag is set to 1, it can read the data in the receive buffer, thus completing a mutual communication process. Here, dsPIC30F6014 is set as the master controller, ISD4002 is set as the slave device, and the communication control process is completed through the SPI port.

SPI bus protocol

SPI is a ring bus structure , consisting of ss (cs), sck, sdi, and sdo. Its timing is actually very simple. It mainly exchanges data between two bidirectional shift registers under the control of sck.
       Assume that the following 8-bit register contains the data to be sent 10101010, which is sent on the rising edge, received on the falling edge, and the high bit is sent first.
       Then when the first rising edge comes, the data will be sdo=1; register=0101010x. When the falling edge comes, the level on sdi will be stored in the register, so at this time the register=0101010sdi, so that after 8 clock pulses, the contents of the two registers are exchanged once. This completes one 

Design of SPI functional module

According to the function definition and the working principle of SPI, the entire IP Core is divided into 8 sub-modules: uC interface module, clock division module, transmit data FIFO module, receive data FIFO module, state machine module, transmit data logic module, receive data logic module and interrupt form module.

In-depth analysis of the four SPI transmission protocols shows that according to one protocol, the remaining three protocols can be obtained by converting the serial synchronous clock. In order to simplify the design regulations, if multiple data are to be transmitted continuously, an idle wait of the serial clock is inserted between two data transmissions, so that the state machine only needs two states (idle and working) to work correctly.