Analysis of s3c2440 address allocation hardware connection and its startup principle

1.CPU address allocation:

1. The memory controller of s3c2440A has the following features:

l Big and small endian (selected by software)

l Address space: 128M bytes per bank (1G bytes/8 banks in total)

l Programmable access bit width, bank0 (16/32 bits), other banks (8/16/32 bits)

l A total of 8 memory banks

l 6 are ROM, SRAM and other types of memory banks (bank0 ---- bank5)

l 2 can be used as ROM, SRAM, SDRAM and other memory banks (bank6 ---- bank7)

l 7 fixed memory bank start addresses (bank0 ---- bank6)

The start address of the last bank can be adjusted (bank7, when two sdrams are connected. The sdram connected to bank7 will be adjusted according to the end address of bank6)

The last two banks are programmable in size

l The access cycle of all memory banks is programmable

The bus access cycle can be extended by inserting an external wait

l Support SDRAM self-refresh and power-down mode

Theoretically, the CPU is 32 bits. The addressable space is 2 to the power of 32, which is 4GB of address space. However, our CPU only uses a little more than 1GB of space, and the rest of the space is not used. Let's take a look at the following figure to make a perceptual understanding:

                                                                       figure 1

(1) The memory manager of S3C2440A provides all control signals for accessing external memory, including 27-bit address signal (ADDR[26:0]), 32-bit data signal (DATA[31:0]), 8 chip select signals (nGCS[7:0]), and read/write control signals.

Looking at Figure 1, we know that starting from address 0x4000 0000, there are on-chip SRAM, on-chip registers, and unused space. These are all fixed and cannot be moved. The only address space left for us users is 0x0000 0000 to 0x3FFF FFFF, which is 1GB. We need 30 address lines to fully address 1GB of address space, 2 The 30th power is exactly equal to 1GB, but only 27 addresses (ADDR[26:0]) are given on the chip pins. With only 27 pins on the chip, it can only control 128M of space. Where do the three wires go? In fact, these three wires are used at the input of the 3-8 decoder (such as: 000 represents 00000001, 001 represents 00000010, 010 represents 00000100, 011 represents 00001000, etc.), and the output of this 3-8 decoder corresponds to nGCS0~7, corresponding to 8 banks, which is used to select which bank is currently in. The advantage of this is that it is very modular and easy to manage. It will not cause a piece of manual address segmentation.

(2) Bank0---bank5 is fixed at 128MB, and the capacity of bank6 and bank7 can be changed programmably, which can be 2, 4, 8, 16, 32, 64, 128MB

Please see Figure 2

                                                                   figure 2

So, the starting address of 7 fixed memory banks (bank0-bank6). The starting address of bank7 is connected to the ending address of bank6, but the capacity of the two must be equal. The minimum supported by s3c2440 is 2MB (2MB per piece, only connected to bank6) and the maximum supported is 256MB (bank6 connected to 128MB, bank7 connected to 128MB). Another point to note is that if two sdrams need to be connected, the capacity of the two pieces must be the same. See Figure 2 for details.

(3) Bank0 can be used as a boot ROM. Its data line width can only be 16 bits and 32 bits, while the data line width of other memories can be 8 bits, 16 bits, and 32 bits.

(4) Address:

0x0000 0000 ----- 0x3FFF FFFF: 8 banks are allocated, each bank has 128MB addressing space, each bank also has a chip select signal, the addresses of these 8 banks are provided to nandflash, norflash, and sdram (the access to sdram will be explained in detail below)

0x4000 0000 ----- 0x47FF FFFF: The first 4KB of the space, that is, 0x4000 0000 to 0x4000 1000, is the on-chip SRAM address space, which is the so-called steppingstone (the role of steppingstone will be discussed below when s3c2440 is started), and the rest of the space is unused.

0x4800 0000 ----- 0x5FFF FFFF : Special function registers, CPU registers are defined and configured at this time.

0x6000 0000 ----- 0xFFFF FFFF : This approximately 3G of space is not used.

2.s3c2440 wiring rules:

                                                 image 3

1) SDRAM connection rules, divided into three steps (taking K4S561632E as an example):

1-1). Need to get the selected IO of the logical bank:

                                  Pic 4-1

                                    Figure 4-2

Bank Size: External memory capacity (K4S561632E is 4M*16bit*4Bank*2Chips/8=64MB)

Bus Width: Bus width (two 16-bit K4S561632E chips, connected in parallel to form 32 bits)
Base Component: Single chip capacity (bit) (256Mb)
Memory Configuration: Memory configuration ((4M*16*4banks)*2Chips)

According to the K4S561632E specification (Figure 4-1, Figure 4-2), we can get some information. Combined with Figure 3, we can get the selection of logical bank I/OA [25:24]

1-2). Need to get the starting pin number of the chip:

                                                       Figure 5

We chose two K4S561632E sdrams, so they are 32-bit. Starting from A2, 

ADDR2 of s3c2440 ------------- A0 of K4S561632E

ADDR3 of s3c2440 ------------- A1 of K4S561632E

And so on...

Why do we start with ADD2? We know that the addressing principle of SDRAM is a storage array, as shown in Figure 6:

                               Figure 6

Each K4S561632E has 4 logical banks, each bank has 4M storage cells, and each storage cell has 16 bits. This is what the specification says: 4M*16bit*4Bank = 256Mbit.

Two K4S561632E chips have 4M*4Bank*32bit = 512Mbit = 64MB. (There are very few 32-bit single-chip SDRAMs on the market, so generally two 16-bit SDRAMs are selected to expand to 32-bit width.)

When the memory is addressed once, the row (ROW) and column (Column) are crossed once to get a storage unit, that is to say, the memory is in units of "storage unit (4 bytes in this case, the lower 16 bits and the upper 16 bits are combined into one storage unit)", not "byte". However, the CPU addressing is in units of bytes. That is to say, the CPU moves to the next one byte, while in this case, the memory moves to the next one 4 bytes. This is why we often say that byte alignment is required when we write programs. Let me give an example to explain it in detail:

CPU addresses memory Memory is returned to CPU

0000 0000 Unit 0 (actually contains 4 bytes from 0000 0000 to 0000 0011)

0000 0100 The first unit (actually contains 4 bytes from 0000 0100 to 0000 0111)

0000 1000 The second unit (actually contains 4 bytes from 0000 1000 to 0000 1011) Because s3c2440 does not connect A1 and A0, it is equivalent to logical AND 0xFFFF FF00, and after fetching the 4 bytes of memory, the lower two bits are used to select

0000 1100 The third unit (actually contains 4 bytes from 0000 1100 to 0000 1111) 

And so on.....

The second bit of the CPU corresponds to the 0th bit of the memory. That is to say, the CPU is 4, and the memory is 1. Their units are different, one is a byte, and the other is a storage unit, that is, the bit width.

Similarly, the A0 of the 16-bit wide SDRAM should be connected to the ADDR1 of the s3c2440.

Conclusion: The pin to which SDRAM A0 is connected to S3C2440 is determined by the bit width of the entire SDRAM.

1-3). Start connecting SDRAM to s3c2440:

                                                          Figure 7

2) Norflash connection rules, taking EN29LV160A as an example.

The bit width of this IC is selected by the high and low levels of pin number 47 to select BYTE/WORD, that is, there are 8-bit and 16-bit modes.

                        Figure 8

                                Fig. 9

The rules are pretty much the same, so I won't go into detail here.

3.NANDFLASH connection rules, taking K9FXX08 as an example:

3.s3c2440 system startup:

S3C2440 supports two boot modes: NAND and non-NAND (here is NOR flash).
The specific mode is determined by the two pins OM0 and OM1.

OM[1:0] determines the startup mode

When OM[1:0]=00, the processor boots from NAND Flash

When OM[1:0]=01, the processor boots from a 16-bit ROM

When OM[1:0]=10, the processor boots from a 32-bit wide ROM.

When OM[1:0]=11, the processor starts from Test Mode.

1 When one of the pins OM0 and OM1 is high, address 0 will be mapped to the external nGCS0 chip select space, that is, Norflash, and the program will be started from Norflash, and arm will directly fetch the instructions in Norflash to run.

2 When both OM0 and OM1 are low, the internal bootbuf (a 4k SRAM) at address 0 will start. When the system is powered on, arm will automatically copy the first 4K content in NANDflash to bootbuf (that is, address 0), and then run from address 0.

The startup of ARM starts from address 0, but the address mapping is different. When the ARM is powered on, if you want the ARM to know how to run in a certain way (address mapping), it is impossible to control it through a program you wrote, because your program has not started yet. At this time, the ARM will judge by the level of the pin.

1) When booting from NorFlash, the NorFlash connected to nGCS0 is mapped to the Bank0 space of nGCS0 chip select, and its address is mapped to 0x0000 0000;

2) When booting from NandFlash, a 4K BootRAM called "Steppingstone" inside the S3C2440 chip is mapped to the Bank0 space of nGCS0 chip select, and its address is mapped to 0x0000 0000. When the system is powered on or reset, the program will start executing from address 0x0, so the boot code we write must be stored at address 0. If the size of all the programs in the system after compilation and linking is less than 4K, then there is no need to consider the issue of moving the programs from NandFlash to SDRAM in the system startup code, because all the programs are copied from NandFlash to BootSRAM at startup, and the programs can be run in BootSRAM; if the size of all the programs in the system after compilation and linking is greater than 4K, then the system startup code needs to include a section of code to move all the programs in the system from NandFlash to SDRAM, because only the first 4K of NandFlash is copied to BootSRAM when the system starts, and some programs are in NandFlash, and the programs cannot run in NandFlash, so all programs need to be copied to SDRAM and run in it, so the system startup code must include this section of code related to program copying, and after all programs are copied, the programs jump to SDRAM to run. That is to say, when NandFlash is started, it is necessary to consider the two moves involved. The first move is automatically implemented by the S3C2440 hardware mechanism, and no intervention is required. The second move needs to be implemented by the programmer, and the size of the moved program is all the programs in the system.

The NANDFLASH startup process is shown in the figure: