S3C2440 Architecture

This article is a study of the ARM processor architecture, targeting the S3C2440 model. It refers to the content of the PROGRAMMER'S MODEL section in Samsung's official technical document S3C2440.pdf.

ARM and THUMB instruction modes

S3C2440 uses armv4t instruction set, and supports both arm instruction set and thumb instruction set. Arm instruction is 32-bit, while thumb instruction is 16-bit. The reason for thumb instruction is to reduce the storage space of code.

Switching between two instruction sets

• Manual switching 
  is because no matter whether it is the arm instruction set or the thumb instruction set, the lowest bit of the code address is redundant, because thumb is 16-bit aligned and arm is 32-bit aligned. So the last bit can be used as a reference for switching. When executing the BX instruction, if the last bit of the address is set, the following instructions are interpreted using the thumb instruction set. When jumping, the last bit is cleared and the arm instruction set is used.

• Automatic switching 
  can only use the arm instruction set in privileged mode, so when executing thumb instructions in user mode, if you jump to privileged mode, it will automatically switch to the arm instruction mode. When switching back to user mode from privileged mode, if the thumb instruction set was used before entering, it will automatically switch back to the thumb instruction set.

Data storage format 
S3C2440 supports both big-endian and small-endian data storage formats. By default, the little-endian format is used for storage.

• Big-endian storage 
  stores high bytes in low addresses and low bytes in high addresses.

• Little endian storage 
  high bytes are stored in high addresses and low bytes are stored in low addresses.

Operation Mode

ARM920T supports seven operation modes:

• User Mode

• Fast interrupt mode

• Interrupt Mode

• Manager Mode

• Abort Mode

• System Mode

• Undefined mode

Mode switching can be done by software or automatically, such as when an interrupt occurs. Except for user mode, all other modes are privileged modes, and some resources can only be used in privileged mode.

register

The ARM920T has a total of 37 registers, and not all registers are visible at the same time.

Registers in ARM mode

Registers in thumb mode

In thumb mode, not all registers are used, and registers R8-R12 are not used.

Although the R8-R12 registers cannot be used in thumb mode, the compiler can use these registers as fast storage.

Status Register

CPSR and SPSR are two status registers in ARM920T. SPSR is used to temporarily save the value of the CPSR register.

Function of the status register

• Save the most recent ALU calculation information

• Controlling interrupts on and off

• Set the processor mode

Exception handling

In ARM, all events that interrupt the normal execution of the program are called exceptions, and interrupts are also exceptions. When entering an exception, the hardware will automatically perform the following operations; but when exiting an exception, the following operations are implemented by our own software.

Entering an exception

1. Save the next instruction address in the appropriate LR register (whichever exception occurs will be saved in the LR register in that mode).

2. Copy the CPSR to the appropriate SPSR (whichever exception occurs will be saved in the SPSR register in that mode).

3. Set the mode bit in CPSR

4. PC gets the address from the corresponding interrupt vector table

Exit abnormally

1. Subtract an offset from the value in LR and assign it to PC

2. Copy the value of SPSR to CPSR

3. If the interrupt prohibition flag is set upon entry, clear the prohibition flag

for example:

HandleIRQ:
    sub lr, lr, #4 @ Calculate the return address
    stmdb sp!, { r0-r12,lr } @ Save the used registers
                                    @ Note that the sp at this time is the sp in interrupt mode
                                    @ The initial value is 3072 set above

    ldr lr, =int_return @ Set the return address after calling ISR, namely EINT_Handle function  
    ldr pc, =EINT_Handle @ Call interrupt service function, int_return in interrupt.c:
    ldmia sp!, { r0-r12,pc }^ @ interrupt return, ^ means copy the value of spsr to cpsr12345678910

The interrupt pending bit needs to be cleared in the interrupt handling function EINT_Handle.

The following table shows the return functions that need to be executed when exiting various exceptions:

Interrupt vector table address

The following table shows the addresses of the interrupt vector table. These addresses are specified and cannot be changed by yourself.

Exception Priority

When multiple exceptions occur simultaneously, there is a fixed priority to determine which one is executed first.

high priority

1. Reset
2. Data abort 
3. FIQ
4. IRQ
5. Prefetch abort123456

Low Priority

6. Undefined Instruction, Software interrupt