Design of Sine Signal Generator for Interface Circuit between AD9850 and Single Chip Microcomputer

　　1 Introduction

　　With the development of digital large-scale integrated circuit technology, direct digital frequency synthesis technology (DDS) using digital circuits has the advantages of fast frequency conversion speed, high frequency resolution, controllable phase, high frequency stability, etc. Signal sources with fast frequency conversion speed and high frequency resolution are indispensable in modern electronic communications, aerospace, automatic control and other fields, so DDS signal sources are widely used in the above fields.

　　AD9850 is one of the typical products of low-power direct digital frequency synthesis technology produced by ADI. AD9850 has the advantages of fast frequency conversion speed, high frequency resolution, low phase noise, high frequency stability, etc. This paper designs a sine wave signal generator with the direct frequency synthesis (DDS) device AD9850 and MCS-51 microcontroller as the core, with necessary peripheral interface devices, under the control of microcontroller software, which can generate additional modulation information of given frequency and starting phase.

　　2. Basic working principle of AD9850

　　2.1 Main performance indicators of AD9850

　　①The maximum supported clock frequency is 125MHz

　　②Frequency resolution reaches 0.029Hz

　　③Support two power supply voltages: +3.3Vor+5V

　　④Low power consumption: 380mW@125MHz (+5V)

　　155mW@110MHz（+3.3V）⑤Frequency conversion time: 10 clock cycles. For example, when fs=125MHz, the frequency conversion time is: 10& TI mes;1/(125& TI mes;106)≈0.1

　　⑥ The output spurious-free dynamic range SFDR is greater than 50dB@40MHz

　　⑦With phase controllable

　　⑧Support parallel port and serial port input control interface

　　⑨The frequency control word uses 32-bit binary code

　　2.2AD9850 Pin Description

　　AD9850 adopts advanced CMOS technology and adopts 28-pin SSOP surface mount package. Its pins are shown in Figure 1 and the pin functions are shown in Table 1.

　　2.3 AD9850 internal structure

　　The chip functional block diagram of AD9850 is shown in Figure 2.

　　The AD9850 chip includes high-speed DDS, 10-bit DAC, frequency/phase data register, data input register, comparator, etc. Under the reference clock of 125MHz, AD9850 can generate a 32-bit frequency adjustment control word through the high-speed DDS core chip to make the output frequency of AD9850 reach 0.0291Hz; and can provide 5 bits of phase control bit, which can change the output phase by 180°, 90°, 45°, 22.5°, 11.25° or any combination of them. The circuit structure of AD9850 allows the output with a frequency value of half of the reference clock, and the output frequency can be changed at a speed of 23,000,000 new frequencies per second by digital control. The comparator in the AD9850 chip can receive the DAC conversion output after external low-pass filtering, and can generate a low-jitter square wave output, so AD9850 is very convenient to use as a clock generator. Frequency/phase data register. The data input register inputs and updates the frequency control word under the control of the external frequency update clock and word loading clock, so that the chip outputs the required frequency and phase.

　　2.4 Working Principle of AD9850

　　AD9850 contains a programmable DDS system and a high-speed comparator, which can realize frequency synthesis under full digital programming control.

　　The programmable DDS system consists of a phase accumulator and a sine lookup table. The phase accumulator consists of an adder and an N-bit phase register, where N is generally 24 to 32. It is essentially a variable modulus counter, that is, the number of DDS phase increments is stored when the counter receives each clock pulse. When the counter overflows, it returns to the initial state and uses the phase accumulator to output to the adjacent value. The frequency control word can set the modulus of the counter, which determines the size of the phase increment. The phase increment is added in the phase accumulator when each clock arrives. The larger the phase increment, the faster the accumulator overflows and the higher the output frequency generated.

　　AD9850 uses a 32-bit phase accumulator. AD9850 uses an improved and unique algorithm to convert the output of the 14-bit truncated phase accumulator into an appropriate cosine value. Through the on-chip high-speed 10-bit DAC converter, an analog sine wave can be obtained. This unique algorithm uses a simplified ROM table and DSP technology and other functions to help reduce the size and power consumption of AD9850. Input. Output. The relationship between the reference clock and the frequency control word is as follows:

　　3. System hardware design

　　3.1 Overall system design

　　The system uses the single-chip microcomputer 8051 as the control core, and the frequency control word and phase control word inside the AD9805 are programmed by software, and then the sine wave signal with the required performance index is achieved through an external low-pass filter.

　　The system is divided into two modules: the single-chip minimum system and the DDS module. The single-chip minimum system includes 8051 single-chip microcomputer, 2*2 interrupt keyboard matrix, serial port communication, and download interface.

　　The DDS module includes the core chip AD9850 and a low-pass filter. The overall system block diagram is shown in Figure 3.

　　3.2AD9850 and MCU interface

　　The following points need to be considered when interfacing AD9850 with a microcontroller:

　　① AD9850 control word writing method selection. There are two ways to write the AD9850 control word: serial and parallel. The advantage of the parallel writing method is that the data transmission speed is fast, which can improve the processing speed of the entire system. In order to give full play to the high-speed performance of the chip, the parallel method should be selected as much as possible when the microcontroller resources allow. Therefore, this system uses the 8051 microcontroller as the control core and controls the AD9850 chip by writing the control word in parallel. As shown in Figure 4, the data lines D0~D7 of the AD9850 are connected to the P1 port.

　　②FQUD and WCLK are connected to the microcontroller. The FQUD control signal and WCLK control signal of AD9850 are connected to P3.0 (pin 10) and P3.1 (pin 11) of the 8051 microcontroller respectively. All timing relationships can be achieved through software control.

　　③RESET is connected to the microcontroller. The crystal oscillator of AD9850 uses 100MHz, and the reset (RESET) signal of AD9850 is valid at high level, and the pulse width is not less than 5 reference clock cycles. Since the high level time of the microcontroller using a 12MHz crystal oscillator can meet the reset requirements of AD9850, the reset terminal of AD9850 can be directly connected to the reset terminal of the microcontroller.

　　3.3 Matters needing attention when applying AD9850

　　① When the AD9850 is used as a clock generator, in order to avoid aliasing or harmonic signals falling into the useful output frequency band and reduce the requirements for external filters, the output frequency must be less than 33% of the reference clock frequency.

　　②The minimum reference clock frequency of AD9850 is 1MHz. If the frequency is lower than this, the system automatically enters power sleep mode; if the frequency is higher than this, the system returns to normal.

　　③ The printed circuit board should be a multi-layer board with a dedicated power layer and ground layer, and there should be no etched conductors that cause layer discontinuity.

　　④ A ground plane with a certain gap should be left on the top layer of the printed circuit board to facilitate surface-mounted devices.

　　⑤ Digital signal lines cannot be placed under the AD9850 device on the printed circuit board to avoid coupling noise into the chip; avoid crossing digital signals and analog signals, and their traces on opposite sides of the circuit board should be perpendicular to each other to reduce the feedthrough effect of the circuit board.

　　⑥ Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other devices on the circuit board, and should never be close to the reference input or under the package.

　　⑦ Consider using a good decoupling circuit and connect high-quality ceramic decoupling capacitors to their respective ground leads - the decoupling capacitors should be as close to the device as possible.

　　⑧ Use independent analog power supply and digital power supply. The AD9850 power supply line should use as wide a trace as possible to provide a low impedance path and reduce the impact of burr noise on the power supply line.