IC that implements delayed system reset at power-on

　　By adding some capacitors, diodes and resistors to the transistor and using a reset IC with adjustable hold time, a purely manual reset can be converted to an automatic reset.

　　In most applications, the (manual reset) pin is usually connected to a switch to generate a manual reset signal for the management chip. It then resets from an active low state back to a high state after a preset active delay time. Manual reset is suitable for most applications; however, it requires human intervention to generate the reset signal. In some applications, manual reset is controversial because it must be performed every time the system is powered on.

　　Furthermore, applications including embedded processors require the reset output to be held high—that is, inactive—for a period of time before a reset is applied or asserted low. The circuit shown in Figure 1 has proven effective without the need to press the reset button when the device is powered on, because the reset automatically occurs with a preset hold time before the reset low signal arrives.

　　The circuit uses a reset management chip with a pin and a low-active output . The internal pull-up resistor of the input is usually 20 to 50 kΩ. During power-up, the internal resistor charges capacitor C1 to the maximum positive value VDD. To generate a reset input for the management chip, its input must receive a low-active ground signal, which requires transistor Q1 to turn on. The length of this turn-on time is determined by the RC time constant of R1 and C2. These two devices determine when Q1 turns on, thereby providing a high level with an adjustable hold time for the output. To increase the hold time, increase the RC time constant of R1 and C2.

The time constant is sufficient.

　　The reset manager chip generates an output only when the voltage on the pin exceeds the trigger threshold voltage and the manager's internal reset cycle ends . This delay time filters out any spikes in the input voltage. Because Q1 is turned on, the negative side of C1 goes to ground. The positive side of C1 cannot change polarity immediately, so it is pulled low and slowly recharged through the internal pull-up resistor of the input. When the threshold voltage of the reset chip is reached, the reset signal is output once the chip delay time is reached. The choice of C1 is not critical. However, its value should be as large as possible - for example, 0.1 to 10µF - so that the RC time constant formed by C1 and the internal pull-up resistor is large enough. This value ensures that C1 maintains a low level at the pin for at least 1us.

　　C2充电到Q1的偏置电压后，晶体管仍然导通。在下一次上电或手动按键复位电路时，晶体管C2放电。这个动作一旦发生，Q1关闭。R1将C1的负向充电到供电电压VDD。因为电容C1的正向不能立即改变，其表现为充电到2VDD。然而，保护二极管D1将C1的电压箝位到仅为VDD加上二极管的导通电压。一旦C2充电足够使Q1再次导通时，重复循环。

　　Original English:

　　IC performs delayed system reset upon power-up

　　By adding a transistor with some caPACitors, diodes, and resistors, you CAN transform a pure-manual reset to an automatic reset with adjustable hold time for the reset IC.

　　Goh Ban Hok, Infineon Technologies Asia Pacific Ltd, Singapore; Edited by Charles H Small and Fran Granville -- EDN, 2/7/2008

　　In most applications, the  (manual-reset) PIN usually connects to a switch to create a manual-reset signal to the supervisory Chip. Subsequently, after a predetermined time-out-active period, it goes back to the high state in an active-low reset. A manual reset is a good feature for most applications; however, it requires human intervention to create the reset. In some applications, a manual reset could be a hassle because you must perform it each time the system powers up.

　　Further, applications involving embedded microprocessors can require the reset output to hold high—that is, inactive—for a certain period of time before you can apply the reset, or active low. The circuit in Figure 1 proves usefulduring power-up when there is no need to press the reset button once the device powers up, because reset oCCurs automatically with the predetermined hold time before you apply the reset-low signal.