Using ARM9 microcontroller to implement upper control algorithm analysis solution

　　introduction

　　In many embedded control systems, the system must complete a large amount of information collection and complex algorithms, and also realize precise control functions. The ARM9 microcontroller running the embedded Linux operating system is used to complete signal collection and implement the upper-level control algorithm, and send the upper-level algorithm to the DSP chip to obtain control parameters. The DSP chip realizes precise and reliable closed-loop control based on the obtained parameters and the lower-level control algorithm.

　　1 Multi-machine system composition

　　The multi-machine control system is based on the ARM9 microcontroller s3c2440 as the core, and uses the I2C bus to mount multiple DSP chips TMS320F28015 as co-controllers, which constitute the core of the entire control system.

　　1.1 Introduction to S3C2440 and TMS320F28015

　　Samsung's processor S3C2440 is a 32-bit microcontroller that integrates ARM's ARM920T processor core. It is rich in resources, with independent 16 KB instruction cache and 16 KB data cache, and the highest main frequency can reach 400 MHz. It has 130 general-purpose I/Os, 24 external interrupt sources and rich external interfaces to realize various functions, including I2C bus interface that supports multi-master function, 3-way URAT, 2-way SPI, camera interface, etc.

　　TMS320F28015 (hereinafter referred to as F28015) is a 32-bit processor of TI. It has powerful control and signal processing capabilities and can implement complex control algorithms. It integrates Flash memory, I2C bus module, fast A/D converter, enhanced CAN bus module, event manager, orthogonal encoding circuit interface and multi-channel buffered serial port and other peripherals on the chip. This integration can easily realize functional expansion. At the same time, the fast interrupt response enables it to protect key registers and respond to external asynchronous events quickly (smaller interrupt delay).

　　1.2 I2C bus interface

　　The I2C bus is a serial bus used to connect IC devices. It uses two lines, SDA (data line) and SCL (clock line), to connect each device or module with an I2C bus interface. The serial 8-bit bidirectional data transmission rate can reach 100 kb/s in standard mode and 400 kb/s in fast mode. Multiple microcontrollers can be easily connected together through the I2C bus interface to form a system, and each device can be identified according to the address. This bus structure has fewer wires and connecting pins, a simple bus between devices, and a compact structure. Therefore, the cost of forming the system is low, and adding devices to the bus will not affect the normal operation of the system. All I2C bus devices share a set of buses, so the system modification and scalability are good.

　　The bus must be controlled by the host (usually a microcontroller), which generates a serial clock (SCL) to control the data transmission of the bus and generate start and stop conditions. The data state on the SDA line can only change when SCL is low. When SCL is high, the change of SDA state is used to indicate the start and stop conditions. The start and stop timing of the I2C bus is shown in Figure 1.

Figure 1 I2C bus start and stop timing

　　1.3 Hardware Circuit

　　Both S3C2440 and F28015 have integrated I2C bus modules, support multi-master I2C bus serial interface, and can be easily connected to the I2C bus. Therefore, the design of the I2C bus interface circuit between the two becomes very simple, just connect the corresponding pins I2C_CLK (corresponding to the SCL line in the I2C bus) and I2C_SDA (corresponding to the DATA line in the I2C bus) of the two. The hardware interface circuit of S3C2440 and TMS320F28015 is shown in Figure 2.

Figure 2 Hardware interface between S3C2440 and TMS320F28015

　　The PA55 and PA56 pins of the circuit S3C2440 correspond to I2C_SDA and I2C_CLK respectively, and the GPIO32 and GPIO33 of the F28015 can also be multiplexed as I2C_SDA and I2C_CLK respectively. Considering that factors such as impedance mismatch will affect the bus data transmission effect, when the I2C_DATA and I2C_CLK pins of the two chips are directly connected, a small resistor is connected in series on each direct connection line .

　　I2C_SDA and I2C_CLK are bidirectional circuits and must be connected to the positive power supply voltage through a current source or a pull-up resistor . Since the output high level of S3C2440 and F28015 is 3.3 V, the I2C_SDA and I2C_CLK buses are connected to the 3.3 V V CC power supply through pull-up resistors during hardware design .

　　2 ARM and DSP communication software design

　　The ARM microcontroller running the Linux operating system as the main controller has significant advantages in data management and multi-task scheduling, and can well organize the data collected by peripheral devices; it mainly realizes the overall control of the system, and controls the I2C bus module through the bus device driver, and realizes the data transmission and reception to the lower-level DSP mounted on the I2C bus through host addressing. In order to ensure the real-time nature of data communication, F28015 realizes data reception and transmission through interrupt response.

　　By configuring the I2C module register of F28015, setting the I2C module to slave mode, and using the I2C bus interrupt response program to receive and send data on the bus, data communication is completed. After F28015 generates an I2C bus interrupt, the interrupt service program is executed. Figure 7 shows the I2C bus interrupt service program flow.

　　The interrupt service program obtains the interrupt type code by querying the flag bit of the status register (I2CSTR), and then calls the corresponding subroutine to complete data reception and transmission. The code is as follows:

　　interrupt void i2c_int1a_isr(void) {//I2CA interrupt response function

　　Uint16 IntSource; // Read interrupt code

　　IntSource=I2caRegs.I2CI SRC .bit.I NTC ODE & 0x7; //I2CA interrupt source, read the last 3 bits

　　switch(IntSource){//Determine the relevant receiving and sending strategies according to the interrupt source

　　case I2C_NO_ISRC://=0

　　case I2C_ARB_ISRC://=1

　　case I2C_NACK_ISRC： //=2

　　case I2C_ARDY_ISRC： //=3

　　case I2C_SCD_ISRC://=6

　　case I2C_AAS_ISRC://=7

　　break;

　　case I2C_RX_ISRC://=4, receiving data is ready

　　DataReceive(); //Call the data receiving sub-function to receive data

　　break;

　　case I2C_TX_ISRC://=5, data transmission is ready

　　DataTransmit(); //Call the data transmission sub-function to receive data

　　break;

　　default:

　　asm("ESTOP0"); //Stop if invalid data

　　}

　　Pie CTR lRegs.PIEACK.all=PIEACK_GROUP8;

　　}

　　The data receiving subroutine and data sending subroutine in F28015 are called according to different status codes in the interrupt service program of the I2C bus. They are the core part of the entire communication program. The flow of the data receiving subroutine and the data sending subroutine is shown in Figure 8.

Figure 8 Data receiving and sending subroutines

　　3 Test Results

　　The I2C bus driver and device driver compiled into modules are loaded onto the S3C2440 platform running the Linux operating system through the NFS file system (the bus driver is loaded first), and then the F28015 test program is burned into the RAM. Run F28015 to wait for data on the I2C bus, and then execute the I2C bus test program in the Linux system. The test results show that the chip completes data communication through the I2C bus interface, with good real-time performance and reliability.

　　4 Conclusion

　　This design uses the I2C bus to achieve real-time and reliable data communication between the ARM9 microcontroller and the DSP chip. The ARM9 microcontroller combines the Linux operating system as the upper control core, and the DSP chip implements the lower control algorithm, which can give full play to the advantages of the ARM9 microcontroller in data acquisition and task management, as well as the advantages of the DSP chip in algorithm implementation and bottom-level control.