Address pointer and its application in 51 single chip microcomputer programming

The address space of the external RAM of the CS-51 microcontroller is 64K, and the address bus is 16 bits. The following four instructions can be executed to access the external RAM:

MOVX A,@DPTR

MOVX @DPTR,A

MOVX A,@RI

MOVX@RI,A

DPTR is a 16-bit address register, the upper 8 bits of the address are stored in DPH, and the lower 8 bits of the address are stored in DPL; Ri (I=0,1) is an 8-bit register, which only stores the lower 8 bits of the address when used as an address pointer.

The MCS-51 executes the above instructions in two stages: First, the instruction code is taken out from the external program memory and analyzed. Then, the data read/write operation to the external RAM is performed. In these two stages, the address selection on the P0 port and the P1 port is different.

When executing the "MOVX A, @DPTR" and "MOVX @DPTR, A" instructions, in the stage of reading the instruction code, the program counter (PC) provides A0~A15. After the low 8-bit address is stable, under the action of the microcontroller address latch signal ALE, the P0.X port begins to read the MOVX instruction code. In the stage of reading and writing to the external RAM, the process is the same as above, except that the low 8-bit address does not come from the low 8-bit PCL of the program counter, but from the high 8-bit DPH of the address register; the high 8-bit address does not come from the high 8-bit PCH of the program counter, but from the high 8-bit PCH of the address register. When DPL is stable, it is latched by the address latch, and the data information of reading/writing the external RAM appears on the P0.X port.

When executing "MOVX A, @Ri" and "MOVX @RI, A", the instruction fetching stage is exactly the same as "movx a, @ dptr" and "movx @ dptr, a". However, when executing the read/write stage to the external RAM, the lower 8-bit address comes from Ri; the upper 8-bit address comes from the P2 port latch (P2 SFR).

As mentioned above, the indirect addressing of the external RAM with R0 and R1 can be regarded as a page addressing, and the current page address is determined by the current value of the P2 latch (P2 SFR). When the MCS-51 microcontroller is reset, the P2 SFR is FFH. If the value in the P2 SFR is not changed during the program running, R0 and R1 can only indirectly address the external RAM in the range of FF00H~FFFFH, that is, FF page addressing. Since changing the value of P2 SFR with instructions does not affect the normal operation of the program, R0 and R1 can be used to indirectly address any unit in the 64K external RAM space. In this way, the address pointer of the MCS-51 microcontroller's external RAM changes from 1 to 3, which greatly facilitates program design.

The following uses the data block transfer subroutine as an example to illustrate the programming method of R0 and R1 indirect addressing of external RAM. Assuming that the source address of the data block is 1000H, the destination address is 3045H, and the data block length is 50H, the program list is as follows:

Program 1—Using DPTR as an address pointer

MOV R2,#00H

MOV R3,#10H

MOV R4,45H

MOV R5,#30H

MOV R7,#50H

LOOP: MOV DPL,R2

MOV DPH,R3

MOVX A,@DPTR

INC DPTR

MOV R2,DPL

MOV R3,DPH

MOV DPL,R4

MOV DPH,R5

MOVX @DPTR,A

INC DPTR

MOV R4,DPL

MOV R5,DPH

DJNZ R7,LOOP

RET

Program 2—Using R0 and R1 as address pointers

MOV DPTR,#1000H

MOV P2,#30H

MOV R0,#45H

MOV R7,#50H

LOOP: MOVX A,@DPTR

MOVX @R0,A

INC DPTR

INC R0

DJNZ R7,LOOP

RET

Program 1 uses 19 instructions, and Program 2 uses 10 instructions. Appropriate use of R0 and R1 address pointers can greatly improve program running efficiency.

In the external RAM data transfer operation using the R0 and R1 indirect addresses, the "MOV P2, #ADDR" and "MOV A, @RI" forms are generally used, where #ADDR is the high 8-bit address. Instructions for changing the P2 SFR value should not be inserted between these two instructions. There are two situations for reading the P2 port: one is to read the P2 latch, such as executing the "MOV A, P2" instruction, which does not change the content in the P2 SFR; the other is to read the P2 latch, such as executing the "INC P2" instruction, in which P2 is both the source operand and the destination operand, which is usually called a "read-modify-write" instruction, that is, the content is read from the P2 SFR, and then written to the P2 SFR after modification.

In the interrupt service program, if the address pointer is to be used, the address pointer used must be protected in the protection field program segment, that is, using the "PUSH P2" and "PUSH Ri" instructions. Before the interrupt returns, the used address pointer must be restored in the recovery field program segment, that is, using the "POP RI" and "POP P2" instructions.

When the MCU enters the waiting mode or power saving mode, and returns to the original normal operation state by hardware reset, the page address is changed because the reset writes FFH to P2 SFR. Therefore, before the MCU enters the waiting mode or power saving mode, the content of P2 SFR must be protected. When the state is restored to the original normal operation program entry, the content of P2 SFR is restored.