Analysis and summary of abnormal interrupt problems in ARM

    1. Types of abnormal interrupts in ARM:
    Abnormal interrupt name meaning Reset (Reset)
    When the processor reset pin is valid, the system generates a reset abnormal interrupt, and the program jumps to the reset abnormal interrupt handler for execution. Reset abnormal interrupts are usually used in the following situations:
    1. When the system is powered on
    2. When the system is reset
    3. Jump to the reset interrupt vector for execution, which is called soft reset
    Undefined instruction When the ARM processor or the coprocessor in the system believes that the current instruction is undefined, an undefined instruction abnormal interrupt is generated. Floating-point vector operations can be simulated through this abnormal interrupt mechanism.
    Software interrupt
    (softwareinterruptSWI)
    This is an interrupt instruction defined by the user. It can be used for programs in user mode to call privileged operation instructions. In the real-time operating system (RTOS), this mechanism can be used to implement system function calls.
    Instruction prefetch abort
    (PrefechAbort)
    If the address of the processor prefetch instruction does not exist, or the address does not allow the current instruction to access, when the prefetched instruction is executed, the processor generates an instruction prefetch abort exception interrupt.
    Data access abort
    (DataAbort)
    If the target address of the data access instruction does not exist, or the address does not allow the current instruction to access, the processor generates a data access abort exception interrupt. External interrupt request (IRQ) When the processor's external interrupt request pin is valid and the I control bit of the CPSR register is cleared, the processor generates an external interrupt request (IRQ) exception interrupt. The peripherals in the system usually request the processor to service the fast interrupt request (FIQ) through this exception interrupt. When the processor's external fast interrupt request pin is valid and the F control bit of the CPSR register is cleared, the processor generates an external interrupt request (FIQ) exception interrupt
    . Note: Do not confuse the exception interrupt type with the processor's operating mode.
    After a reset exception occurs, enter the management mode (svc). After a soft interrupt occurs, enter the management mode (svc). After an undefined instruction exception occurs, the processor enters the undefined instruction abort mode (und). After an instruction prefetch abort exception occurs, the processor enters the data access abort mode (abt); After a data access abort exception occurs, the processor enters the data access abort mode (abt): After an external interrupt occurs, the processor enters the external interrupt mode (irq); After a fast interrupt occurs, the processor enters the fast interrupt mode (fiq); II. ARM's response process to abnormal interrupts
    (1) ARM processor's response process to abnormal interrupts:
    Save the processor's current state, interrupt mask bit, and each condition flag bit. This is achieved by saving the contents of the current program status register CPSR to the SPSR register corresponding to the abnormal interrupt to be executed. Each abnormal interrupt has its own physical SPSR register. Set the corresponding bit in the current program status register CPSR. Including: entering the ARM state; setting the bit in the CPSR to make the processor enter the corresponding execution mode; setting the bit in the CPSR to disable the IRQ interrupt. When entering the FIQ mode, the FIQ interrupt is disabled. Set the register Ir_mode (R14) to the return address. Set the program counter value (PC) to the interrupt vector address of the exception interrupt, so as to jump to the corresponding exception interrupt handler for execution.
    Note: The above process is all completed automatically by hardware. Regardless of whether an exception occurs in ARM state or THUMB state, it will automatically switch to ARM state for exception processing
    
    
    (2) Return from the exception interrupt handler:
    restore the processor state of the interrupted program, that is, copy the contents of the SPSR_mode register to the CPSR. Return to the next instruction of the instruction where the exception interrupt occurred, that is, copy the contents of the Ir_mode register to the program counter PC.
    Note: In fact, when an exception interrupt occurs, the location pointed to by the program counter PC is different for different exception interrupts. Similarly, the return address is different for various exception interrupts. For details, see (3) The
    reset exception interrupt handler does not need to return. The reset exception interrupt handler starts the execution of the entire user program, so it does not need to return. Due to the different exception modes and the use of pipeline technology in the ARM core, the return address must be calculated according to the exception mode in the exception handler. The execution of an instruction is divided into three main stages: instruction fetch, decoding, and execution. Because the CPU uses pipeline technology, the address of the currently executed instruction should be PC-8 (four bytes for one instruction on a 32-bit machine), so the next instruction to be executed should be PC-4. When an exception occurs, the CPU will automatically save the value of PC-4 to LR, but whether the value is correct depends on the type of exception.
    (3) Details: After each abnormal state occurs, the ARM processor hardware response process
    
    
    1. Response to reset abnormal interrupt
    Power-on reset: After power-on, reset makes the internal reach a predetermined state, especially the program jumps to the initial entry; reset pulse on the reset pin: This is caused by other external control signals; overvoltage or undervoltage is detected in the system power supply; clock abnormal reset.
    When a reset occurs, the processor hardware responds to the interrupt and automatically performs the following operations:
    Force entry into management mode; Force entry into ARM state; Disable IRQ interrupts and FIQ interrupts; Jump to absolute address PC = 0x00000000 to execute
    2. Undefined instruction exception
    An instruction that cannot be executed is encountered. This instruction is not defined; Execute an operation instruction for the coprocessor. Under normal circumstances, the coprocessor should respond, but the coprocessor does not respond.
    After the processor responds to the interrupt, the hardware automatically performs the following operations:
    Copy the program status register CPSR to SPSR_und; Force entry into undefined mode; Force entry into ARM mode; Disable IRQ interrupts Copy the address of the next instruction to LR; Jump to absolute address PC = 0x00000004 to execute About
    the return from the exception interrupt handler:
    The undefined instruction exception interrupt is generated by the currently executed instruction itself. When the interrupt occurs, the value of the program counter PC has not been updated. It points to the second instruction after the current instruction (for ARM instructions, it points to the current instruction address plus 8 bytes; for Thumb instructions, it points to the current instruction address plus 4 bytes). When an undefined instruction exception interrupt occurs, the processor automatically saves the value (pc-4) to lr_und. At this time, (pc-4) points to the next instruction of the current instruction, so the return from the undefined instruction exception interrupt can be implemented through the following instructions:
    MOVPC,LR
    When the data stack is used in the exception interrupt handler, the following instructions can be used to save the execution scene of the interrupted program when entering the exception interrupt handler, and restore the execution scene of the interrupted program when exiting the exception interrupt handler. The data stack used in the exception interrupt program is provided by the user.
    STMFDsp!,{reglist,lr}
    ....
    LDMFDsp!,{reglist,pc}^
    reglist is a list of registers used in the exception interrupt handler. The identifier ^ indicates that the contents of the SPSR_mode register are copied to the CPSR. This instruction can only be used in privileged mode.
    
    
    3. The software interrupt exception
    is caused by the instruction SWI. After the program executes this instruction, it enters the exception interrupt.
    After the processor responds to the interrupt, the hardware automatically performs the following operations:
    copy the program status register CPSR to SPSR_svc; force entry into management mode; force entry into ARM state; disable IRQ interrupt. Copy the address of the next instruction to LR; jump to the absolute address PC = 0x00000008 for execution;
    
    
    about the return from the exception interrupt handler:
    the software interrupt exception is generated by the currently executed instruction itself. When the interrupt occurs, the value of the program counter PC has not been updated. It points to the second instruction after the current instruction (for ARM instructions, it points to the current instruction address plus 8 bytes; for Thumb instructions, it points to the current instruction address plus 4 bytes). When a software interrupt occurs, the processor automatically saves the value (pc-4) to lr_siw. At this time, (pc-4) points to the next instruction of the current instruction, so returning from the software interrupt can be achieved through the following instructions:
    MOVPC,LR
    When the data stack is used in the exception interrupt handler, the following instructions can be used to save the execution site of the interrupted program when entering the exception interrupt handler, and restore the execution site of the interrupted program when exiting the exception interrupt handler. The data stack used in the exception interrupt program is provided by the user.
    STMFDsp!,{reglist,lr}
    ....
    LDMFDsp!,{reglist,pc}^
    
    
    reglist is the register list used in the exception interrupt handler. The identifier ^ indicates that the contents of the SPSR_mode register are copied to the CPSR. This instruction can only be used in privileged mode.
    
    
    4. Prefetch abort exception The
    abort exception caused by the program memory is called the prefetch abort exception; the abort exception caused by the data memory is called the data abort exception. Since the ARM instruction is a 3-stage pipeline structure, the instruction reading cycle is performed in advance, so the process of reading instructions is generally called prefetch. During instruction prefetching, if the target address is illegal, the instruction is marked as a problematic instruction. At this time, the instruction before the instruction on the pipeline continues to execute. There are two possibilities as follows:
    1. When the program jumps before executing this instruction, this invalid instruction does not cause an abnormal interrupt; 2. When this instruction is executed, the processor will generate a prefetch abort exception, causing an interrupt.
    After the processor responds to the interrupt, the hardware automatically performs the following operations:
    copy the program status register CPSR to SPSR_abt; force to enter the abort exception mode; force to enter the ARM state; disable IRQ interrupt. Copy the address of the PC at the time of the interrupt to LR; jump to the absolute address PC=0x0000000C for execution;
    Regarding the return from the abnormal interrupt handler:
    During instruction prefetching, if the target address is illegal, the instruction is marked as a problematic instruction. At this time, the instruction before the instruction on the pipeline continues to execute. When the instruction marked as problematic is executed, the processor generates an instruction prefetch abort exception interrupt. When an instruction prefetch exception interrupt occurs, the program should return to the problematic instruction, re-read and execute the instruction, so the instruction prefetch abort exception interrupt should return to the instruction that generated the instruction prefetch abort exception interrupt, rather than the next instruction of the current instruction.
    The instruction prefetch exception is generated by the currently executed instruction itself. When the interrupt occurs, the value of the program counter PC has not been updated. It points to the second instruction after the current instruction (for ARM instructions, it points to the current instruction address plus 8 bytes; for Thumb instructions, it points to the current instruction address plus 4 bytes). When the instruction prefetch abort exception interrupt occurs, the processor automatically saves the value (pc-4) to lr_abt. At this time, (pc-4) points to the next instruction of the current instruction, so returning from the software interrupt can be achieved by the following instruction:
    SUBSPC, LR, #4
    When the data stack is used in the exception interrupt handler, the following instruction can be used to save the execution scene of the interrupted program when entering the exception interrupt handler, and restore the execution scene of the interrupted program when exiting the exception interrupt handler. The data stack used in the exception interrupt program is provided by the user.
    SUBSLR, LR, #4
    STMFDsp!, {reglist, lr}
    ....
    LDMFDsp!, {reglist, pc}^
    reglist is the register list used in the exception interrupt handler. The identifier ^ indicates that the contents of the SPSR_mode register are copied to the CPSR. This instruction can only be used in privileged mode.
    
    
    5. Data abort exception
    When the ARM processor accesses the data memory, the data memory sends an abort signal while reading the data, causing a data abort exception. If the target address of the data access instruction does not exist, or the address is not allowed to be accessed by the current instruction, the processor generates a data access abort exception interrupt.
    
    
    After the processor responds to the interrupt, the hardware automatically performs the following operations:
    copy the program status register CPSR to SPSR_abt; force to enter the abort exception mode; force to enter the ARM state; disable IRQ interrupt; copy the address of the PC at the time of interruption to LR; jump to the absolute address PC = 0x00000010 to execute.
    Regarding the return from the exception interrupt handler:
    When a data access exception interrupt occurs, the program must return to the problematic instruction and re-access the data. Therefore, the data access exception interrupt should return to the instruction that generates the data access abort exception interrupt, rather than the next instruction of the current instruction. The data access exception interrupt is generated when the currently executed instruction is executed in the ALU. When the data access exception interrupt occurs, the value of the program counter pc has been updated, and it points to the third instruction after the current instruction (for ARM instructions, it points to the current instruction address plus 12 bytes; for Thumb instructions, it points to the current instruction address plus 6 bytes). At this time, the processor saves the value (pc-4) into lr_abt, which points to the second instruction after the current instruction, so the return operation can be implemented by the following instruction:
    SUBSPC,LR,#8
    When the data stack is used in the exception interrupt handler, the following instruction can be used to save the execution scene of the interrupted program when entering the exception interrupt handler, and restore the execution scene of the interrupted program when exiting the exception interrupt handler. The data stack used in the exception interrupt program is provided by the user.
    SUBSLR,LR,#8
    STMFDsp!,{reglist,lr}
    ....
    LDMFDsp!,{reglist,pc}^
    reglist is a list of registers used in the exception interrupt handler. The identifier ^ indicates that the contents of the SPSR_mode register are copied to the CPSR. This instruction can only be used in privileged mode.
    
    
    6. Interrupt request (IRQ) exceptions
    , such as timer interrupts, serial port communication interrupts, external signal interrupts, and A/D processing interrupts. IRQ interrupts are maskable. The I bit in the status register is the mask bit of IRQ. When I=1, the IRQ interrupt is masked, and when I=0, the interrupt is enabled. After the processor is reset, I is set to 1 to disable the interrupt. After the processor responds to the interrupt, the hardware automatically performs the following operations: copy the program status register CPSR to SPSR_irq; force to enter the IRQ exception mode; force to enter the ARM state; disable IRQ interrupt; copy the address value of PC at the time of interrupt to LR; jump to the absolute address PC = 0x00000018 to execute;
    about the return from the exception interrupt handler:
    usually after the processor executes the current instruction, it queries the IRQ interrupt pin and checks whether the system allows IRQ interrupts. If an interrupt pin is valid and the system allows the interrupt to occur, the processor will generate an IRQ exception interrupt. When the IRQ exception interrupt occurs, the value of the program counter pc has been updated, and it points to the third instruction after the current instruction (for ARM instructions, it points to the current instruction address plus 12 bytes; for Thumb instructions, it points to the current instruction address plus 6 bytes). When the IRQ exception interrupt occurs, the processor saves the value (pc-4) to the register lr_irq in the IRQ exception mode, which points to the second instruction after the current instruction. Therefore, the correct return address can be calculated by the following instruction:
    SUBSPC, LR, #4
    When the data stack is used in the exception interrupt handler, the following instructions can be used to save the execution site of the interrupted program when entering the exception interrupt handler, and restore the execution site of the interrupted program when exiting the exception interrupt handler. The data stack used in the exception interrupt program is provided by the user.
    SUBSLR, LR, #4
    STMFDsp!, {reglist, lr}
    ....
    LDMFDsp!, {reglist, pc}^
    reglist is the register list used in the exception interrupt handler. The identifier ^ indicates that the contents of the SPSR_mode register are copied to the CPSR. This instruction can only be used in privileged mode.
    Note: Why does PC point to the last 12 bytes of the currently executed instruction?
    When the current instruction is executed (PC points to the second instruction after the current instruction), if an IRQ interrupt occurs, after ARM detects the IRQ interrupt, the instruction fetch and execution units will not change, only the decoding unit will change, and the decoding unit will start decoding the interrupt instruction instead. After executing the current instruction, the PC value is increased by 4 bytes (PC now points to the third instruction after the previous instruction), and the decoding unit sends the decoded interrupt instruction to the execution unit. The execution unit executes the interrupt instruction, saves the value of PC-4 (PC now points to the second instruction after the current instruction) to LR_irq, and jumps to the IRQ interrupt vector. (For details, see ARM pipeline mechanism
    
    
    7, fast interrupt (FIQ) request exception.
    FIQ fast interrupt is maskable. The F bit in the status register is the mask bit of FIQ. When F=1, the FIQ interrupt is masked, and when F=0, the interrupt is allowed. After the processor is reset, F is set to 1 to turn off the interrupt. After the processor responds to the interrupt, the hardware automatically performs the following operations:
    copy the program status register CPSR to SPSR_fiq; force entry into FIQ exception mode; force entry into ARM state; disable FIQ interrupt; copy the address value of PC at the time of interrupt to LR; jump to the absolute address PC=0x0000001C to execute;
    
    
    about returning from the exception interrupt handler:
    usually after the processor executes the current instruction, it queries the FIQ interrupt handler. pin, and check whether the system allows FIQ interrupts. If an interrupt pin is valid and the system allows the interrupt to occur, the processor will generate a FIQ exception interrupt. When the FIQ exception interrupt occurs, the value of the program counter pc has been updated, and it points to the third instruction after the current instruction (for ARM instructions, it points to the current instruction address plus 12 bytes; for Thumb instructions, it points to the current instruction address plus 6 bytes). When the FIQ exception interrupt occurs, the processor saves the value (pc-4) to the register lr_fiq in the IRQ exception mode, which points to the second instruction after the current instruction. Therefore, the correct return address can be calculated by the following instruction:
    SUBSPC, LR, #4
    When the data stack is used in the exception interrupt handler, Chengdu Design Company recommends that the following instructions can be used to save the execution site of the interrupted program when entering the exception interrupt handler, and restore the execution site of the interrupted program when exiting the exception interrupt handler. The data stack used in the exception interrupt program is provided by the user.
    SUBSLR, LR, #4
    STMFDsp!, {reglist, lr}
    ....
    LDMFDsp!, {reglist, pc}^
    reglist is a list of registers used in the exception interrupt handler. The identifier ^ indicates that the contents of the SPSR_mode register are copied to the CPSR. This instruction can only be used in privileged mode.
    Note: Why does PC point to the last 12 bytes of the currently executed instruction?
    When the current instruction is executed (PC points to the second instruction after the current instruction), if a FIQ interrupt occurs, after ARM detects the FIQ interrupt, the instruction fetch and execution units will not change, only the decoding unit will change, and the decoding unit will start decoding the interrupt instruction instead. After executing the current instruction, the PC value is increased by 4 bytes (PC points to the third instruction after the previous instruction), and the decoding unit sends the decoded interrupt instruction to the execution unit. The execution unit executes the interrupt instruction, saves the value of PC-4 (PC points to the second instruction after the current instruction) to LR_fiq, and jumps to the FIQ interrupt vector at the same time. (For details, see the ARM pipeline mechanism)