pic16f877a.h Chinese comments

Storage path: In the PICC software hi-tech installation directory, ?:\Microchip\cc8.05\include, find pic1687xa.h, which contains
the following header file content and detailed comments:

/*
 * Header file for the Microchip 
 * PIC 16F873A chip
 * PIC 16F874A chip
 * PIC 16F876A chip
 * PIC 16F877A chip
 * Midrange Microcontroller
 */

#if defined(_16F874A) || defined(_16F877A)
#define __PINS_40
#endif

static volatile unsigned char INDF @ 0x00; //Indirect Addressing Register
static volatile unsigned char TMR0 @ 0x01; //Timer 0
static volatile unsigned char PCL @ 0x02; //Low 8-bit Program Counter
static volatile unsigned char STATUS @ 0x03; //Program Status Register
static unsigned char FSR @ 0x04; //Special Function Register
static volatile unsigned char PORTA @ 0x05; //Port A Register
static volatile unsigned char PORTB @ 0x06; //Port B Register
static volatile unsigned char PORTC @ 0x07; //Port C Register
#ifdef __PINS_40
static volatile unsigned char PORTD @ 0x08; //Port D Register
static volatile unsigned char PORTE @ 0x09; //Port E Register
#endif
static unsigned char PCLATH @ 0x0A; //High 5-bit program counter
static volatile unsigned char INTCON @ 0x0B; //Interrupt control register
static volatile unsigned char PIR1 @ 0x0C; //Interrupt flag register PIR1
static volatile unsigned char PIR2 @ 0x0D; //Interrupt flag register PIR2
static volatile unsigned char TMR1L @ 0x0E; //Low byte count register
static volatile unsigned char TMR1H @ 0x0F; //High byte count register
static volatile unsigned char T1CON @ 0x10; //TMR1 control register
static volatile unsigned char TMR2 @ 0x11; //Timer/Counter TMR2
static volatile unsigned char T2CON @ 0x12; //TMR2 control register
static volatile unsigned char SSPBUF @ 0x13; //Receive/transmit data buffer
static volatile unsigned char SSPCON @ 0x14; //Synchronous serial port control register, set and define the functions and indicators of the MSSP module
static volatile unsigned char CCPR1L @ 0x15; //Capture/Compare/PWM register low byte
static volatile unsigned char CCPR1H @ 0x16; //Capture/Compare/PWM register low byte
static volatile unsigned char CCP1CON @ 0x17; //CCP1CON register
static volatile unsigned char RCSTA @ 0x18; //USART receive control and status register
static volatile unsigned char TXREG @ 0x19; //USART generation buffer
static volatile unsigned char RCREG @ 0x1A; //USART receive buffer
static volatile unsigned char CCPR2L @ 0x1B; //Capture/Compare/PWM register low byte
static volatile unsigned char CCPR2H @ 0x1C; //Capture/Compare/PWM register low byte
static volatile unsigned char CCP2CON @ 0x1D; //CCP2CON register
static volatile unsigned char ADRESH @ 0x1E; //ADC conversion result register high byte
static volatile unsigned char ADCON0 @ 0x1F; //A/D converter switch bit

/* bank 1 registers */
static unsigned char bank1 OPTION @ 0x81; //Select register to configure TMR0/WDT prescaler coefficient, external INT interrupt, TMR0 and weak pull-up of port B.
static volatile unsigned char bank1 TRISA @ 0x85; //Port A direction register
static volatile unsigned char bank1 TRISB @ 0x86; //Port B direction register
static volatile unsigned char bank1 TRISC @ 0x87; //Port C direction register
#ifdef __PINS_40
static volatile unsigned char bank1 TRISD @ 0x88; //Port D direction register
static volatile unsigned char bank1 TRISE @ 0x89; //Port E direction register
#endif
static volatile unsigned char bank1 PIE1 @ 0x8C; //Interrupt enable register PIE1
static volatile unsigned char bank1 PIE2 @ 0x8D; //Interrupt enable register PIE2
static volatile unsigned char bank1 PCON @ 0x8E; //Power control status register
static volatile unsigned char bank1 SSPCON2 @ 0x91; //MSSP control register 2
static volatile unsigned char bank1 PR2 @ 0x92; //TMR2 period register
static volatile unsigned char bank1 SSPADD @ 0x93; //Synchronous serial port address register
static volatile unsigned char bank1 SSPSTAT @ 0x94; //Synchronous serial port status register
static volatile unsigned char bank1 TXSTA @ 0x98; //USART generation control and status register
static volatile unsigned char bank1 SPBRG @ 0x99; //USART baud rate generator initial value register
static volatile unsigned char bank1 CMCON @ 0x9C; //Comparison control register
static volatile unsigned char bank1 CVRCON @ 0x9D; //Comparison voltage reference control register
static volatile unsigned char bank1 ADRESL @ 0x9E; //ADC conversion result register low byte
static volatile unsigned char bank1 ADCON1 @ 0x9F; //ADC control register ADCON1

/* bank 2 registers */
static volatile unsigned char bank2 EEDATA @ 0x10C; //EEPROM data register low byte
static volatile unsigned char bank2 EEADR @ 0x10D; //EEPROM address register low byte
static volatile unsigned char bank2 EEDATH @ 0x10E; //EEPROM data register high byte
static volatile unsigned char bank2 EEADRH @ 0x10F; //EEPROM address register high byte

/* bank 3 registers */
static volatile unsigned char bank3 EECON1 @ 0x18C; //EEPROM control register 1
static volatile unsigned char bank3 EECON2 @ 0x18D; //EEPROM control register 2

//* STATUS bits status register */
static volatile bit IRP @ (unsigned)&STATUS*8+7; //Register bank select bit (for indirect addressing). 0:bank0,1;1:bank2,3
static volatile bit RP1 @ (unsigned)&STATUS*8+6; //Register bank select bit (for direct addressing)
PR1:PR0:00:BANK0;01:BANK1;10:BANK2;11BANK3.
static volatile bit RP0 @ (unsigned)&STATUS*8+5; //
static volatile bit TO @ (unsigned)&STATUS*8+4; //Timeout bit. 0: WDT timeout occurs; 1: After power-on, CLRWDT or SLEEP instruction is executed
static volatile bit PD @ (unsigned)&STATUS*8+3; //Power-off flag. 0: After executing the SLEEP instruction; 1: After power-on or executing the CLRWDT instruction
static volatile bit ZERO @ (unsigned)&STATUS*8+2; //Zero flag. 0: The result of an arithmetic or logical operation is not 0; 1: On the contrary.
static volatile bit DC @ (unsigned)&STATUS*8+1; //Digital carry/borrow flag. 0: No carry occurred in the lower 4 bits of the result; 1: On the contrary.
static volatile bit CARRY @ (unsigned)&STATUS*8+0; //Carry/borrow flag. 0: No carry occurred in the upper 4 bits of the result; 1: On the contrary.

/*      PORTA bits      */
static volatile bit RA5 @ (unsigned)&PORTA*8+5;   //RA5
static volatile bit RA4 @ (unsigned)&PORTA*8+4;   //RA4
static volatile bit RA3 @ (unsigned)&PORTA*8+3;   //RA3
static volatile bit RA2 @ (unsigned)&PORTA*8+2;   //RA2
static volatile bit RA1 @ (unsigned)&PORTA*8+1;   //RA1
static volatile bit RA0 @ (unsigned)&PORTA*8+0;   //RA0
 
/*      PORTB bits      */
static volatile bit RB7 @ (unsigned)&PORTB*8+7;   //RB7
static volatile bit RB6 @ (unsigned)&PORTB*8+6;   //RB6
static volatile bit RB5 @ (unsigned)&PORTB*8+5;   //RB5
static volatile bit RB4 @ (unsigned)&PORTB*8+4;   //RB4
static volatile bit RB3 @ (unsigned)&PORTB*8+3;   //RB3
static volatile bit RB2 @ (unsigned)&PORTB*8+2;   //RB2
static volatile bit RB1 @ (unsigned)&PORTB*8+1;   //RB1
static volatile bit RB0 @ (unsigned)&PORTB*8+0;   //RB0

/*      PORTC bits      */
static volatile bit RC7 @ (unsigned)&PORTC*8+7;   //RC7
static volatile bit RC6 @ (unsigned)&PORTC*8+6;   //RC6
static volatile bit RC5 @ (unsigned)&PORTC*8+5;   //RC5
static volatile bit RC4 @ (unsigned)&PORTC*8+4;   //RC4
static volatile bit RC3 @ (unsigned)&PORTC*8+3;   //RC3
static volatile bit RC2 @ (unsigned)&PORTC*8+2;   //RC2
static volatile bit RC1 @ (unsigned)&PORTC*8+1;   //RC1
static volatile bit RC0 @ (unsigned)&PORTC*8+0;   //RC0

/*      PORTD bits      */
#ifdef __PINS_40          
static volatile bit RD7 @ (unsigned)&PORTD*8+7;   //RD7
static volatile bit RD6 @ (unsigned)&PORTD*8+6;   //RD6
static volatile bit RD5 @ (unsigned)&PORTD*8+5;   //RD5
static volatile bit RD4 @ (unsigned)&PORTD*8+4;   //RD4
static volatile bit RD3 @ (unsigned)&PORTD*8+3;   //RD3
static volatile bit RD2 @ (unsigned)&PORTD*8+2;   //RD2
static volatile bit RD1 @ (unsigned)&PORTD*8+1;   //RD1
static volatile bit RD0 @ (unsigned)&PORTD*8+0;   //RD0

/*      PORTE bits      */
static volatile bit RE2 @ (unsigned)&PORTE*8+2;   //RE2
static volatile bit RE1 @ (unsigned)&PORTE*8+1;   //RE1
static volatile bit RE0 @ (unsigned)&PORTE*8+0;   //RE0
#endif

//* INTCON bits interrupt control register */
static volatile bit GIE @ (unsigned)&INTCON*8+7; //General interrupt enable bit. 0: Mask all interrupt requests; 1: Allow non-maskable interrupts.
static volatile bit PEIE @ (unsigned)&INTCON*8+6; //External interrupt enable bit. 0: Disable; 1: Enable
static volatile bit T0IE @ (unsigned)&INTCON*8+5; //TMR0 overflow interrupt enable bit. 0: Disable; 1: Enable
static volatile bit INTE @ (unsigned)&INTCON*8+4; //RB0/INT external interrupt enable bit. 0: Disable; 1: Enable.
static volatile bit RBIE @ (unsigned)&INTCON*8+3; //RB port change interrupt enable bit. 0: Disable; 1: Enable.
static volatile bit T0IF @ (unsigned)&INTCON*8+2; //TMR0 overflow interrupt flag. 0: No overflow; 1: Overflow.
static volatile bit INTF @ (unsigned)&INTCON*8+1; //RB0/INT external interrupt flag. 0: RB0 external interrupt did not occur; 1: RB0 external interrupt occurred.
static volatile bit RBIF @ (unsigned)&INTCON*8+0; //RB port change interrupt flag. 0: No change in RB port; 1: At least one pin of RB port has changed.
// alternate definitions
static volatile bit TMR0IE @ (unsigned)&INTCON*8+5; //
static volatile bit TMR0IF @ (unsigned)&INTCON*8+2; // 

//* PIR1 bits interrupt flag register PIR1 */
#ifdef __PINS_40
static volatile bit PSPIF @ (unsigned)&PIR1*8+7; //Parallel slave port read and write interrupt flag. 0: No read or write operation occurs; 1: Otherwise
#endif
static volatile bit ADIF @ (unsigned)&PIR1*8+6; //A/D converter interrupt flag. 0: A/D conversion is not completed; 1: A/D conversion is completed.
static volatile bit RCIF @ (unsigned)&PIR1*8+5; //USART receive interrupt flag. 0: Receive buffer is empty; 1: Otherwise.
static volatile bit TXIF @ (unsigned)&PIR1*8+4; //USART send interrupt flag. 0: Buffer full occurs; 1: Otherwise.
static volatile bit SSPIF @ (unsigned)&PIR1*8+3; //Synchronous serial port (ssp) interrupt flag. 0: No SSP interrupt condition occurs;
static volatile bit CCP1IF @ (unsigned)&PIR1*8+2; //CCP1 interrupt flag.
static volatile bit TMR2IF @ (unsigned)&PIR1*8+1; //TMR2 TO PR2 match interrupt flag. 0: No match occurs
static volatile bit TMR1IF @ (unsigned)&PIR1*8+0; //TMR1 overflow interrupt flag, 0: No overflow

/* PIR2 bits */
static volatile bit CMIF @ (unsigned)&PIR2*8+6; //Comparator interrupt flag; 0: Comparator input has not changed
static volatile bit EEIF @ (unsigned)&PIR2*8+4; //EEPROM write operation interrupt flag. 0: Write operation is not completed or not started
static volatile bit BCLIF @ (unsigned)&PIR2*8+3; //Bus conflict interrupt flag. 0: No bus conflict occurs
static volatile bit CCP2IF @ (unsigned)&PIR2*8+0; //CCP2 interrupt flag

//* T1CON bits TMR1 control register */
static volatile bit T1CKPS1 @ (unsigned)&T1CON*8+5; //TMR1 input clock prescaler selection bit
static volatile bit T1CKPS0 @ (unsigned)&T1CON*8+4; //TMR1 input clock prescaler selection bit
static volatile bit T1OSCEN @ (unsigned)&T1CON*8+3; //TMR1 oscillator enable control bit. 0: Oscillator off
static volatile bit T1SYNC @ (unsigned)&T1CON*8+2; //TMR1 external clock input synchronization control bit.
static volatile bit TMR1CS @ (unsigned)&T1CON*8+1; //TMR1 clock source selection bit. 0: Internal clock/4
static volatile bit TMR1ON @ (unsigned)&T1CON*8+0; //TMR1 enable bit. 0: Disable

//* T2CON bits TMR2 control register */
static volatile bit TOUTPS3 @ (unsigned)&T2CON*8+6; //TMR2 post-scaler selection bit.
static volatile bit TOUTPS2 @ (unsigned)&T2CON*8+5; //TMR2 post-scaler selection bit
static volatile bit TOUTPS1 @ (unsigned)&T2CON*8+4; //TMR2 post-scaler selection bit
static volatile bit TOUTPS0 @ (unsigned)&T2CON*8+3; //TMR2 post-scaler selection bit.
static volatile bit TMR2ON @ (unsigned)&T2CON*8+2; //TMR2 enable bit.
static volatile bit T2CKPS1 @ (unsigned)&T2CON*8+1; //TMR2 pre-scaler selection bit.
static volatile bit T2CKPS0 @ (unsigned)&T2CON*8+0; //TMR2 pre-scaler selection bit