Marquee/input and output interface (chip select address 74LS273)

;NAME: Marquee
;AUTOR: 
;CONTENT: P1.0～P1.7 connect to light emitting diodes L1～L8 　　　　

     CSEG AT 4000H ; define the starting address, why is it 4000H?
                　　　　　  ;Memory: Program memory, data memory unified addressing, up to 64K, on-board ROM (16K); RAM
                 　　　　　 ; (32K) for user use, expandable to 48k. The user memory starts at 4000H; 8051 original
                 　　　　　 ; The interrupt entry addresses are all located at the corresponding addresses after offset 4000H
     LJMP START 
     CSEG AT 4100H 
START:    
     MOV A, #01H; Light up the first LED first. #01 is chosen because an inverter is added.
 LOOP:     
     MOV P1, A; Output from P1 port to light emitting diode    
       
 DELAY500MS: ; Delay 0.5 seconds 
        MOV R7,#0BH DL1:
        MOV R6,#5CH DL0:
        MOV R5,#7AH DJNZ R5,$ DJNZ R6,DL0 DJNZ R7,DL1 
        RL A; Shift left one position and light up the next LED 
        LJMP  LOOP 
 END

;NAME: Input and output interface (read whether the switch is closed or open);AUTOR: ;TIME: April 12, 2012 18:22:14;CONTENT: P1.0~P1.7 are connected to buttons K1~K8; SO0~SO7 of 74LS273 are connected to light-emitting diodes L1~L8, and the chip select terminal CSU8\ is connected to CS0 (determined by the entry address selected by the program).　

           PORT EQU 0CFA7H ; chip select address CS0 CSEG AT 4000H ; absolute addressing, same as above
           LJMP START 
           CSEG AT 4100H 
START:   
           MOV P1, #0FFH 
LOOP:     
           MOV A, P1; read the switch status from P1 port 
           MOV DPTR, #PORT 
           MOVX @DPTR, A ; Output from 74LS273 to LED 
           LJMP LOOP ; loop END

Connection method of chip select address 74ls172

74LS273 is an 8-bit data/address latch. This example uses 74LS273 to expand the I/O output port. The value on the data bus is latched in 74LS273 through the chip select signal and the write signal, and the data is output at the port of 74LS273. When the value on the data bus is cancelled, since 74LS273 can latch the signal, the output of 74LS273 remains unchanged until new data is latched.

1. Hardware Design

Create a new Design and add the following components (omit the crystal oscillator and reset circuit):

Use 8 light-emitting diodes to display the output data of the microcontroller. When the output is low, the LED lights up. D0~D7 of 74LS273 are 8-bit data input terminals, connected to the P0 port of the microcontroller, Q0~Q7 are 8-bit data output terminals, CLK is the trigger clock input terminal, and MR is the data clear enable terminal. Use OR gate 74LS32 for address decoding. The input terminals of U3:A are connected to the P2.7 port and WR port of the microcontroller respectively, and the output terminal is connected to the CLK port of 74LS273.

From the truth table of 74LS273, we can see that when MR is low, all Q terminals are 0, otherwise the Q terminal is determined by the D terminal, so MR should be set to a high level. CLK completes the data latch operation at the rising edge, so the output of U3:A must complete a change from low to high. When the write instruction is valid, the output is low. Only when P2.7 is low at the same time can a level change from low to high be achieved when the write instruction is completed. In this way, after the write is completed, the data is locked by 74LS273. It can be seen that the address of 74LS273 should be 0XXX XXXX XXXX XXXX, and we usually set it to 7FFF.

2. Programming

In Keil C51, there are the following memory types:

• code is the program memory read by MOVC a, @A+DPTR

• data Internal data memory that can be directly accessed

• idata Internal data memory accessed by Mov @Rn

• bdata Bit addressable internal memory

• xdata External data memory accessed by MOVX @DPTR

• pdata External data memory accessed by MOVX @Rn

For ease of use, a macro definition is provided in the absacc.h file. For example, the address 0x7fff in this example can be written as XBYTE[0x7fff].

#include "at89x51.h"

#include "absacc.h"

#define A74273 XBYTE[0x7fff]

void main(void)

{

    A74273 = 0x2b;

    while(1);  

}

Note: When the write instruction is valid (it should be WR, high when invalid), the output is low level. Only when P2.7 is low level at the same time, can a level change from low to high be realized when the write instruction is completed. In this way, after the write is completed, the data is locked by 74LS273. It can be seen that the address of 74LS273 should be 0XXX XXXX XXXX XXXX, and we usually set it to 7FFF.