LPC1768\1769 interrupt priority and interrupt priority group

1. Background
        After the USB has been communicating for hundreds of thousands of times, the USB IN interrupt may be lost several times. This is because the interrupt priority is not high enough.
    The USB interrupt is queued, but before the queue is completed, a new USB interrupt occurs, causing the interrupt to be lost.
    The default priority is "0" (the lower the number, the higher the priority), so the first solution that can be thought of is to reduce the power of all other devices except USB.
    There are interrupt priorities.
        This article gives an overview of the interrupt priorities and priority groups of LPC1769.
        Note: Except for the maximum supported clock frequency, no other differences have been found between LPC1768 and LPC1769.

2. Main text
        First, let's talk about interrupt priority. All interrupts have a priority level. 1. Lower priority numbers represent higher priority levels. 2. Except for system-level interrupts such as RESET, Hard fault, and NMI, all other interrupt priorities can be configured as "0~31". 
        If the software does not configure the priority of these interrupts, the priority of all interrupts defaults to the highest priority "0".
    An example is used to illustrate the concept of interrupt priority. Assume there are three external interrupts "A, B, C", "A, B" is configured as "0", "C" is configured as "1", 1. If the three interrupts are generated at the same time, then "A, B" interrupts will take priority over "C" interrupt. 2. If "A, B" interrupts are generated at the same time, which one will be executed first? Then according to the order of the interrupt vector table, the lower one will be executed first. 3. If "C" interrupt is running, and "A" interrupt occurs at this time, then "A" interrupt will preempt "C" interrupt execution privileges and take priority.
            4. If the interrupt "A" is running and the interrupt "B" occurs, the newly generated interrupt "B" will enter the waiting state.
            Wait until "A" is executed before executing again.
        The above is just to judge the priority value to control the order of interrupts. In order to enhance the control logic of interrupts, ARM has added a priority
    The concept of group. That is, the same priority level can be assigned to a group of priorities, and sub-priorities can be defined within this group of priorities.
    What is the concept of the system? Or suppose there are four interrupts "A, B, C, D", "A, B, C" are configured in priority group "0", "A, B" interrupts are configured
    Set the priority level to "0", "C" to "1", and "D" to "1".
        1. If "A, D" interrupts occur at the same time, the "A" interrupt with a higher priority will be executed before the "D" interrupt. 2. If "A, C" interrupts occur at the same time, the "A" interrupt with a higher priority will be executed first. 3. If "A, B" interrupts occur at the same time, the interrupt with a lower priority will be executed first according to the position of the interrupt vector table. 4. If "D" is executing an interrupt and "A" interrupt comes, then "A" interrupt will preempt "D" interrupt and execute first. Because "A" is
            5. If "C" is executing an interrupt and "A" comes, then "A" will wait for "C" to finish before executing.
            Same priority group.
        ARM uses an 8-bit register to define the concept of priority groups and sub-priorities. An endpoint can be selected in the middle, and the high bit indicates that there is
    The number of main priorities, the low bit indicates the number of secondary priorities.
        The LPC1769 only uses 5 of them. The details are as follows:

**********************************************************************************

        Taking the endpoint 1768 selected in the above figure as an example, the above figure shows that there are "2^3=8" priority groups, because the upper three bits are used to define the priority.
    Similarly, the lower two bits are used to define the sub-priority level, which is "2^2=4".
        Let me explain this with an example:
        The "core_cm3.h" provided by LPC1769 provides functions for defining priority groups and sub-priority groups.
        Define a priority group function:
        __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) // The PriorityGroup parameter is as written above. Since LPC1769 only uses 5 bits, the parameter range passed in is "2~7" // The corresponding priority group and subpriority are as follows

        // I chose 8 priority groups and 4 sub-priorities. The code is as follows:
        NVIC_SetPriorityGrouping(0x04);
        Next, define the next priority function:
        __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) // Parameter IRQn represents the interrupt vector value, which is defined in the file "LPC17xx.h"
        /** @brief IRQ interrupt source definition */
        typedef enum IRQn
        {            /******  Cortex-M3 Processor Exceptions Numbers ********************/
                ...
                Reset_IRQn                    = -15, 
                ...            
            /******  LPC17xx Specific Interrupt Numbers *************************/
            
                ... 
                USB_IRQn                      = 24,       
                ... 
        } IRQn_Type; // Parameter priority // represents the interrupt priority value, and the range is still "0~31", so we need to calculate the position of the priority group ourselves // For the 8 priority groups I defined, the value "0~3" is priority group "0", "..."28~31" is priority group "7".
        NVIC_SetPriority(USB_IRQn,0); //In priority group "0"
        NVIC_SetPriority(TIMER0_IRQn,4); // In priority group "1"
    This completes the record.