ATmega 16 microcontroller interrupt system related registers (VIII)

Vector number Program address Interrupt source Interrupt definition1
    0x000 RESET External pin level trigger, power-on, power-down detection, watchdog, and JTAG AVR reset2
    0x002 INT0 External interrupt request 0 interrupt3
    0x004 INT1 External interrupt request 1 interrupt4
    0x006 TIMER2 COMP Timer/Counter 2 compare match interrupt5 0x008
    TIMER2 OVF Timer/Counter 2 overflow interrupt6
    0x00A TIMER1 CAPT Timer/Counter 1 Event Capture Interrupt7
    0x00C TIMER1 COMPA Timer/Counter 1 Compare Match A Interrupt8
    0x00E TIMER1 COMPB Timer/Counter 1 Compare Match B Interrupt9
    0x010 TIMER1 OVF Timer/Counter 1 Overflow Interrupt10
   0x012 TIMER0 OVF Timer/Counter 0 Overflow Interrupt11
   0x014 SPI_STC SPI serial transfer end
   interrupt12 0x016 USART_RXC USART receive end interrupt
   13 0x018 USART_UDRE USART data register empty
   14 0x01A USART_TXC USART transmit end interrupt
   15 0x01C ADC ADC conversion end interrupt
   16 0x01E EE_RDY EEPROM ready interrupt
   17 0x020 ANA_COMP Analog comparator interrupt
   18 0x022 TWI Two-wire serial interface interrupt
   19 0x024 INT2 External interrupt request 2 interrupt
   20 0x026 TIMER0_COMP Timer/Counter 0 compare match interrupt
   21 $028 SPM_RDY Save program memory content ready

Determination of reset and interrupt vector locations
BOOTRST IVSEL Reset Address Interrupt Vector Starting Address
       1 0 0x0000 0x0002
       1 1 0x0000 Boot Area Reset Address + 0x0002
       0 0 Boot Reset Address 0x0002
       0 1 Boot Reset Address Boot Area Reset Address + 0x0002

1.MCUCR——MCU Control Register

            SM2 SE SM1 SM0 ISC11 ISC10 ISC01 ISC00

Bit 3, 2 - ISC11, ISC10: Interrupt trigger mode control 1 Bit 1 and bit 0
External interrupt 1 is triggered by pin INT1 if the I flag bit and the corresponding interrupt mask bit of the SREG register are set. The MCU first samples the level on the INT1 pin before detecting the edge. If the edge trigger mode or level change trigger mode is selected, a pulse with a duration greater than one clock cycle will trigger an interrupt, and a pulse that is too short cannot guarantee an interrupt. If the low level trigger mode is selected, the low level must be maintained until the current instruction is executed.

ISC11 ISC10 Description
   0 0 An interrupt request is generated when INT1 is at a low level
   0 1 Any logic level change on the INT1 pin will trigger an interrupt
   1 0 The falling edge of INT1 generates an asynchronous interrupt request
   1 1 The rising edge of INT1 generates an asynchronous interrupt request

Bits 1, 0–ISC01, ISC00: Interrupt 0 trigger mode control Bits 1 and 0
External interrupt 0 is triggered by pin INT0 if the I flag bit and the corresponding interrupt mask bit of the SREG register are set. The MCU first samples the level on the INT0 pin before detecting the edge. If the edge trigger mode or level change trigger mode is selected, a pulse lasting longer than one clock cycle will trigger an interrupt, and a pulse that is too short cannot guarantee an interrupt. If the low level trigger mode is selected, the low level must be maintained until the current instruction is executed.

ISC01 ISC00 Description
    0 0 An interrupt request is generated when INT0 is at a low level
    0 1 Any logic level change on the INT0 pin will trigger an interrupt
    1 0 The falling edge of INT0 generates an asynchronous interrupt request
    1 1 The rising edge of INT0 generates an asynchronous interrupt request

2.MCUCSR——MCU Control and Status Register

            JTD ISC2 – JTRF WDRF BORF EXTRF PORF

Bit 6 - ISC2: Interrupt 2 trigger mode control
Asynchronous external interrupt 2 is activated by external pin INT2 if the I flag in the SREG register and the corresponding interrupt mask bit in the GICR register are set. If ISC2 is written as 0, the falling edge of INT2 activates the interrupt. If ISC2 is written as 1, the rising edge of INT2 activates the interrupt. The edge triggering mode of INT2 is asynchronous. As long as a pulse with a width greater than the data shown in Table 36 is generated on the INT2 pin, an interrupt will be triggered. If a low-level interrupt is selected, the low level must be maintained until the current instruction is completed
before an interrupt will be generated. And as long as the pin is pulled low, an interrupt request will be triggered. Interrupts may occur when changing ISC2. Therefore, it is recommended to clear the corresponding interrupt enable bit INT2 in the GICR register first, and then change ISC2. Finally, don't forget to clear the corresponding interrupt flag bit INTF2 in the GIFR register by writing '1' to it before re-enabling interrupts.

3.GICR——General Interrupt Control Register

          INT1 INT0 INT2 – – – IVSEL IVCE

Bit 7 - INT1: Enable external interrupt request 1
When INT1 is '1' and the I flag of the status register SREG is set, the corresponding external pin interrupt is enabled. The interrupt sensitivity level control 1 bit 1/0 (ISC11 and ISC10) of the MCU general control register - MCUCR determines whether the interrupt is triggered by the rising edge, falling edge, or INT1 level. Once enabled, even if the INT1 pin is configured as an output, as long as the pin level changes accordingly, an interrupt will be generated.
Bit 6 - INT0: Enable external interrupt request 0
When INT0 is '1' and the I flag of the status register SREG is set, the corresponding external pin interrupt is enabled. The interrupt sensitivity level control 0 bit 1/0 (ISC01 and ISC00) of the MCU general control register - MCUCR determines whether the interrupt is triggered by the rising edge, falling edge, or INT0 level. Once enabled, even if the INT0 pin is configured as an output, as long as the pin level changes accordingly, an interrupt will be generated.

Bit 5 - INT2: Enable external interrupt request 2
When INT2 is '1' and the I flag of the status register SREG is set, the corresponding external pin interrupt is enabled. The interrupt sensitivity level control 2 bits 1/0 (ISC2 and ISC2) of the MCU general control register - MCUCR determine whether the interrupt is triggered by the rising edge, falling edge, or INT2 level. As long as it is enabled, even if the INT2 pin is configured as an output, as long as the pin level changes accordingly, an interrupt will be generated.

4.GIFR——General interrupt flag register

              INTF1 INTF0 INTF2 – – – – –

Bit 7 - INTF1: External interrupt flag 1
When the level of the INT1 pin changes, an interrupt request is triggered and the corresponding interrupt flag INTF1 is set. If bit I of SREG and the corresponding interrupt enable bit INT1 of the GICR register are "1", the MCU jumps to the corresponding interrupt vector. The flag is automatically cleared after entering the interrupt service routine. In addition, the flag bit can also be cleared by writing "1".
Bit 6 - INTF0: External interrupt flag 0
When the level of the INT0 pin changes, an interrupt request is triggered and the corresponding interrupt flag INTF0 is set. If bit I of SREG and the corresponding interrupt enable bit INT0 of the GICR register are "1", the MCU jumps to the corresponding interrupt vector. The flag is automatically cleared after entering the interrupt service routine. In addition, the flag bit can also be cleared by writing "1".
Bit 5 - INTF2: External interrupt flag 2
When the level of the INT2 pin changes, an interrupt request is triggered and the corresponding interrupt flag INTF2 is set. If bit I of SREG and the corresponding interrupt enable bit INT2 of the GICR register are "1", the MCU jumps to the corresponding interrupt vector. This flag is automatically cleared after entering the interrupt service routine. In addition, the flag bit can also be cleared by writing "1". Note that when the INT2 interrupt is disabled and entering certain sleep modes, the input buffer of this pin will be disabled. This will cause a logic change in the INTF2 flag setting signal.