Detailed explanation of the s3c2440 startup process

1: s3c2440 is 32-bit, so it can address 4GB of space. Memory (SDRAM), ports (special registers), and ROM are all mapped to the same 4G space.

2: Development boards generally use SDRAM as memory flash (nor, nand) as ROM. Among them, nand flash has no address line, and at least one page (512B) must be read at a time. The other two have address lines

3: NAND flash is not used to run code, but only to store code. NOR flash and SDRAM can run code directly.

4: S3C2440 has 8 memory banks in total.
6 memory banks can be used as ROM or SRAM.
The remaining 2 banks can be used as SDRAM in addition to ROM or SRAM (the read and write methods of various memories are different).
The starting address of 7 banks is fixed.
There is also a flexible bank memory address, and the bank size can also be changed.

5: S3C2440 supports two boot modes: NAND and non-NAND (here is NOR flash).
The specific method used depends on the two pins OM0 and OM1 .

OM[1:0] determines the startup mode

When OM[1:0]=00, the processor boots from NAND Flash

When OM[1:0]=01, the processor boots from a 16-bit ROM

When OM[1:0]=10, the processor boots from a 32-bit wide ROM.

When OM[1:0]=11, the processor starts from Test Mode.

When booting from NAND

The CPU will automatically read the first 4KB of data from NAND flash and place it in the on-chip SRAM (s3c2440 is soc), and map this on-chip SRAM to the nGCS0 chip select space (i.e. 0x00000000). The CPU starts execution from 0x00000000, which is the first 4KB of content in NAND flash. Because NAND FLASH does not even have address lines, it is not possible to directly map NAND to 0x00000000, so the on-chip SRAM has to be used as a carrier. Through this carrier, the large code in nand flash is copied to RAM (usually SDRAM) for execution

When booting from non-NAND flash

Nor flash is mapped to address 0x00000000 (that is, nGCS0, so there is no need for on-chip SRAM to assist, so the starting address of on-chip SRAM is still 0x40000000). Then the CPU starts executing from 0x00000000 (that is, executing in Norfalsh).

Summarize:

The startup of Arm starts from address 0, but the difference is that the address mapping is different. When the arm is powered on, if you want the arm to know how to run in a certain way (address mapping method), it is impossible to control it through a program you wrote, because your program has not started at this time. At this time, the arm will judge by the level of the pin. 

1 When one of the pins OM0 and OM1 is high, address 0 will be mapped to the external nGCS0 chip select space, that is, Norflash, and the program will start from Norflash. The arm directly takes the instructions in Norflash to run. 

2 When OM0 and OM1 are both low, the internal bootbuf (a 4k SRAM) at address 0 starts. When the system is powered on, the arm will automatically copy the first 4K content in NANDflash to bootbuf (that is, address 0), and then run from address 0.

At this time, the first 4K in NANDFlash is the boot code (its function is to initialize the hardware and then copy the code in NANDFlash to RAM, and then point the corresponding pointer to the place where it should run). 

    Why are there these two boot methods? The key is the different characteristics of the two flashes. NOR FLASH has a small capacity, fast speed, good stability, input address, and then give read and write signals to get data from the data port, which is suitable for program storage. NAND FLASH has a large total capacity, but both reading and writing require complex timing, which is more suitable for data storage. This difference causes NORflash to be directly connected to the arm bus and can run programs, while NANDflash must be moved to memory (SDRAM) to run. 

   In actual development, the bootloader can generally be burned into Norflash, and the program can be run through serial port interaction to perform certain operations, such as downloading and debugging. This makes it very convenient to debug some of your code. The Bootloader in Norflash can also burn the kernel to Norflash and other functions.