Design Scheme of CAN Adapter Card Generator Condition Monitor

　　CAN (Controller Area Network) is a serial communication network. It uses many new technologies and unique designs, which makes it have outstanding advantages in reliability, real-time and flexibility. These outstanding performances have enabled the CAN bus to maintain rapid development around the world. Considering the growth of the CAN bus and the fact that many single-chip microcomputers are integrated with CAN bus controllers, and that CAN bus dedicated controller IC technology is easy to obtain on the market, the CAN bus technology is used in the generator status monitor designed by the author.

　　1 Composition mode of CAN bus system

　　The generator condition monitor based on fieldbus consists of three parts: intelligent data acquisition module, industrial computer (IPC), and CAN bus. Its system structure is shown in Figure 1. Each module is connected to an industrial computer system through the CAN bus. The main function of the industrial computer is to set the parameters of the intelligent data acquisition module and obtain the data of the intelligent data acquisition module in real time through the fieldbus network, such as generator event records, fault recording; real-time display of monitoring data, trend analysis, abnormal alarm and report output. The CAN bus part is mainly composed of CAN bus adapter card, communication medium and corresponding communication software

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　　2 Hardware Structure of CAN Smart Adapter Card

　　The excellent performance of the CAN bus provides a guarantee for the high-speed data communication of the generator status monitoring system, but many industrial PCs do not have a CAN bus interface. In order to expand the monitoring and management functions of the CAN bus on the IPC, the author designed an adapter card to be inserted into the expansion slot of the IPC to complete the expansion functions of the CAN interface and the IPC.

　　The hardware circuit of the CAN bus PC adapter card is shown in Figure 2. It mainly includes the 89C52 microcontroller (containing 8K E2PROM, 256 bytes RAM), the address decoding and interrupt signal control logic circuit EPM7128S, the shared memory dual-port RAM (IDT7132), the CAN controller SJA1000 chip and the optoelectronic isolation circuit (6N137) and the CAN driver 82C520.

　　To achieve data transmission between the PC and the CAN controller, a two-way data exchange channel must be established between the PC and the MPC on the card. There are two ways to achieve data exchange between the microcontroller system and the host through the ISA bus: one is static data transmission, which uses parallel interface devices (such as 8255) or latches (such as 74LS373) to form a byte-deep FIFO. This method is relatively simple, but the amount of data transmitted at one time is small, so it is only suitable for occasions with small data volume and low speed requirements; the second is to share the external data storage of the microcontroller system. At this time, the integrated dual-port RAM can be directly used or some control logic can be added to the general RAM to form a dual-port RAM circuit. The integrated dual-port RAM is a high-performance fast-pass device suitable for multi-CPU distributed systems and high-speed digital systems. It provides two completely independent ports, each port has complete address, data and control lines. For the user of the device, it is not much different from the general RAM. Contention only occurs when both sides read and write the same address unit at the same time. Using the dual-port RAM to provide an indication signal and adopting appropriate communication rules can avoid contention and achieve fast data exchange. Integrated dual-port RAM is not only easy to implement, but also inexpensive. CAN signal transmission uses a short frame structure (8 bytes), and the adapter card does not require a large capacity for dual-port RAM, so IDT7130, IDT7132, IDT71231, etc. can be selected. This article uses the 2k×8-bit IDT7132 with a busy signal BUSY. The CAN communication controller uses the SJA1000 produced by Philips, which supports the CAN2.0B protocol and is fully compatible with the 82C200. If it is regarded as a memory-mapped register, it is easy to interface with the 89C52. In order to enhance the differential transmission and reception capabilities of the CAN bus, this design uses the CAN bus transceiver interface circuit 82C250. Connecting an optocoupler between the SJA1000 and the slave's 82C250 can enhance the system's anti-interference ability. The optocoupler can use the high-speed optocoupler 6N137. The optocoupler uses a DC-DC isolated power supply on both sides, and the PS250DC5D5S produced by Liyuan can be selected.

　　3. Cutting method

　　The key to dual-port RAM communication is to handle contention properly and avoid read and write errors. IDT7132 can provide hardware arbitration and use the signal of BUSY pin to improve the flexibility of the system. In the hardware circuit of Figure 2, since IDT7132 contains hardware arbitration circuit and both ports have BUSY pins, when two ports compete for the same address unit, the on-chip hardware circuit can determine which port has the right to use it according to the address, chip select and the order of read and write signals arriving after the selection.

　　It can be seen that the BUSY signal can be directly sent to the READY pin of the CPU that supports inserting the wait sequence, such as the 80C196, without software support. In this card, since the 89C52 does not have a READY signal, the BUSYR signal will be latched when the 89C52 issues a command to read or write IDT7132, and only the value of the P1.6 port can be read to determine whether there is a conflict when reading or writing IDT7132. When the value of P1.6 is 1, there is no conflict in the query just now; when the value of 1.6 is 0, there is a conflict in the query just now. At this time, the command to read and write IDT7132 should be resent. Since the ISA bus has no READY signal and no general I/O pins, the BUSYL signal from the IDT7132 can be connected to the lowest bit D0 of the data line. However, because BUSYL should not be connected to D0 except when querying the BUSYL pin level, the three-state gate 74L125 should be used. BUSYL is connected to the input of the tri-state gate, and the output of the tri-state gate is connected to the ISA bus data line D0. Its gate control signal is generated by A9~A5, so it will occupy an I/O port of the ISA bus. When designing, you should choose an idle port number, here you choose 330H (dual-port RAM side, PC needs to change the code), that is, A9~A5 is decoded to 11001. The specific circuit is shown in Figure 3.

　　4 Adapter Card Software Design

　　The adapter card is mainly used to undertake the task of data forwarding between the host computer and the CAN node.

Its software design also includes two parts: the first part is the application program interface (API) function on the PC side, which is responsible for completing the communication between the PC side and the dual-port RAM. This part can be written using visual programming tools such as C++Builder. The PC side software functions mainly include sending control commands, data commands and request data commands to the dual-port RAM on the adapter card, and post-processing the received data (such as display, reports, etc.); the second part is the program design of the microcontroller on the card, which is responsible for the communication between the microcontroller and the dual-port RAM to dominate the CAN controller. This part can be written in assembly language ASM51 or Franklin C51. The main task of the software design is to forward the commands from the PC to the CAN controller, and the CAN controller further forwards them to the CAN node; at the same time, the data and status information received by the CAN controller from the CAN node are sent to the dual-port RAM.

　　5 Issues that need clarification

　　The CAN protocol specification (CAN Specification 2.0A/B) is only a low-level specification. Therefore, a high-level/application layer protocol is also needed. The capabilities of CAN are selected and limited by the high-level protocol. At present, there are many CAN application layer protocols in the world, such as DeviceNet, CANopen, CAN Kingdom, etc., but users can customize simpler application layer protocols. The task of the application layer protocol is, on the one hand, to classify, disassemble, and merge the data to be sent, and determine the sending object, and then fill in each CAN information frame according to the CAN data link layer protocol specification. On the other hand, it is to interpret the specific meaning of the received data and process it accordingly.