s3c6410 memory map

         2. Internal storage area 

                (1) Internal ROM 0x0800_0000~0x0BFF_FFFF

                (2) Internal SRAM 0x0C00_0000~0x0FFF_FFFF

         3. Static storage area 0x1000_0000~0x3FFF_FFFF

         4. Dynamic storage area 0x4000_0000~0x6FFF_FFFF

The physical memory of S3C6410 is divided into two parts: Memory and Pheriperal, with address ranges of 0x0~0x6fffffff and 0x7fffffff respectively. The system accesses the Memory space through the SPINE bus and the Pheriperal space through the PERI bus. In order to adapt to the access speed of different peripherals, high-speed peripherals such as LCD, Camera, Accelerator are accessed through the AHB bus, and low-speed peripherals such as iic and watchdog are accessed through the APB bus.

3.2 Memory
Memory, also known as main memory, is divided into four major areas, namely the boot image area, internal memory area, static memory area, and dynamic memory area.

The physical address of the boot image area is 0x00000000~0x07ffffff, a total of 128MB. The function of this area is as its name suggests, it is used to start the system. However, there is no actual storage medium corresponding to this range. You can only map the physical address of the corresponding medium to this boot area after selecting the specific boot medium through OM[4:0]. For example, after selecting the IROM boot mode, the address space occupied by IROM is mapped to the space starting from 0x00000000. The

physical address of the internal memory area is 0x08000000~0x0fffffff, a total of 128MB. This area corresponds to the internal memory address, and the internal ROM and SRAM are distributed in this interval. Among them, 0x08000000~0x0bffffff corresponds to the internal ROM. Of course, the internal ROM is not as large as 64MB in reality. Only 32KB has actual storage media. This 32KB is a read-only area, which contains the boot code under the IROM mode. When selecting IROM boot, the first code to run is this part, called BL0, which is fixed by the manufacturer. 0x0c000000~0x0fffffff corresponds to the internal SRAM. According to Samsung's manual, the actual available SRAM is 4KB. In fact, this is the Steppingstone used for nand flash startup (but this Steppingstone is 8KB, the two seem to be contradictory, I don't know if my understanding is wrong).

The physical address of the static memory area is 0x10000000~0x3fffffff, a total of 6*128MB. This area is used to access devices hanging on the external bus, such as SRAM, NOR flash, oneNand, etc. This area is divided into 6 banks, each bank is 128MB, and the maximum data width supports 16 bits. Each bank is demarcated by Xm0CS[5:0]. Unlike S3C2410, bank2~bank5 can be mapped to non-linear memories such as nand flash and CF. This does not mean that the internal addresses of nand flash and CF can be directly accessed through the address segments of bank2~bank5. On the contrary, when mapped to these devices, the addresses of these banks can no longer be used. Access to these non-linear memories still has to be done through the AHB bus of the Pheriperal space, which is the same as the access method in S3C2410. However, there is a special case that when Xm0CS2 is mapped to nand flash, the 4KB (or 8K?) SRAM of Steppingstone is mapped to the 4KB starting from bank2, and when booted in nand flash mode, bank2 is mapped to the starting point of 0x00000000, which actually maps Steppingstone to 0x0000000, which is similar to the situation of S3C2410. The

physical address of the dynamic memory area is 0x40000000~0x6fffffff, a total of 3*256MB. The first 256MB is reserved, and the actual dynamic memory area is 0x50000000~0x6fffffff, which is divided into two intervals, each occupying 256MB. The two intervals can be selected through DMC Xm1CS[1:0]. This memory area is mainly used to expand DRAM, and the maximum DRAM that can be expanded is 512MB.