AVR external interrupt

When the system is running the main program normally, if there is suddenly an important task to be processed immediately, the system will save the current work and then process this task. After completing this important task, it will return to the original main program to continue running. This is an interrupt.

Once the main program enters the interrupt service routine, the AVR chip will automatically turn off the global interrupt, and no other interrupt requests will be executed during this period. The chip will automatically reopen the global interrupt until the interrupt program ends. (Note that during this period, some interrupt requests may be discarded, and some requests will leave interrupt request marks. Once the current interrupt is executed, the request with the interrupt mark may be responded to immediately. For example, the falling edge trigger of INT0 will leave an interrupt request mark, while the low level trigger will not leave an interrupt request mark.) If you want to respond to another more important interrupt while executing the interrupt service routine, you must add a statement to turn on the global interrupt in the interrupt service routine.

Let's discuss external interrupts first.

External interrupts need to remember 5 registers, namely:

1. Status register -SREG status register. And the external interrupt is concerned with its Bit-7-I, global interrupt enable. When set, global interrupt is enabled. Those individual interrupts are the interrupts you want to implement, and their enable is controlled by other independent control registers, such as EIMSK mentioned below. If we clear I to 0, all interrupts will not occur, just like a general switch, even if the individual interrupt flag is set or not. I can be set and cleared by SEI and CLI instructions.

2. External Interrupt Mask Register -EIMSK External interrupt mask register. When INT7 – INT0 is '1', and the I flag of the status register SREG is set, the corresponding external pin interrupt is enabled.

3. External Interrupt Control Register A – EICRA External Interrupt Control Register A. Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sensitivity Level Control Bits. See datesheet for details. If the I flag of the SREG register and the corresponding interrupt mask bit of the EIMSK register are set, then external interrupt 3 - 0 is activated by pins INT3~INT0. It should be noted that when changing ISCn, an interrupt may occur. Therefore, it is recommended to first clear the corresponding interrupt enable bit INTn in EIMSK, and then change ISCn. Finally, don’t forget to re-enable the interrupt by writing “1", clear it to 0.

4. External Interrupt Control Register B – EICRB External Interrupt Control Register B. Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Level Sensitivity Control Bits. See datesheet for details, it is different from EICRA. The MCU samples the INT7:4 pins before detecting the signal transition edge. If the transition edge interrupt or level change interrupt is selected (both rising and falling edges will generate interrupts), the interrupt will occur as long as the signal duration is greater than one clock cycle; otherwise, the interrupt is not guaranteed to be triggered. Note that due to the XTAL divider, the CPU clock may be slower than the XTAL clock. If the low level interrupt is selected, the low level must be maintained until the current instruction is completed before an interrupt is generated. And as long as the pin is pulled low, an interrupt request will be triggered. And, as with EICRA, it is also necessary to note that when changing ISCn1/ISCn0, you must first disable the interrupt by clearing the interrupt enable bit in the EIMSK register. Otherwise an interruption may occur during the change of ISCn1/ISCn0.

5. External Interrupt Flag Register – EIFR. External Interrupt Flag Register. When the level of INT7:0 pin changes, an interrupt request is triggered and the corresponding interrupt flag INTF7:0 is set. If bit I of SREG and the corresponding interrupt enable bit of EIMSK register are '1', the MCU jumps to the interrupt routine. The flag is cleared by hardware when the interrupt routine is executed. In addition, the flag bit can also be cleared by writing '1' If INT7:0 is configured as level trigger, these flags are always '0'In sleep mode, if interrupts are disabled, the input buffers for these pins are also disabled. This may cause a logic level change and set INTF3:0. For more information, refer to the manual "Digital Input Enable and Sleep Mode".

We should be clear that the external interrupt is triggered by the pin INT7:0. As long as the interrupt is enabled, even if the pin INT7:0 is configured as an output, as long as the level changes appropriately, the interrupt will be triggered. This feature can be used to generate software interrupts. By setting the external interrupt control registers – EICRA (INT3:0) and EICRB (INT7:4), the interrupt can be triggered by the falling edge, rising edge, or low level. When the external interrupt is enabled and configured as level-triggered, the interrupt will be generated as long as the pin level is low. If INT7:4 is required to be triggered on the falling or rising edge of the signal, the I/O clock must work, as described in the data sheet P 33 "Clock System and Its Distribution". The interrupt condition detection of INT3:0 is asynchronous. In other words, these interrupts can be used to wake up the device from sleep mode. The I/O clock is stopped during the sleep process (except idle mode).

The above are mostly from the data sheet. Maybe we have some confusion.

1. Why does AVR write "1"It can also be cleared to 0, isn't that strange? You can refer to the following web pages

         http://www.ouravr.com/bbs/bbs_content.jsp?bbs_sn=749852

http://www.ouravr.com/bbs/bbs_content.jsp?bbs_sn=691118&bbs_page_no=1&bbs_id=1000

http://www.c51bbs.com/c51bbs/topic1/c51bbs17322.htm

But in the end, the real reason is in the AVR-GCC help document avr-libc, FAQ24, Why are (many) interrupt flags cleared by writing a logical 1? Of course, your English must be good.

See the following instructions:

Why are (many) interrupt flags cleared by writing a logical 1?

Usually, each interrupt has its own interrupt flag bit in some control register, indicating the specified interrupt condition has been met by representing a logical 1 in the respective bit position. When working with interrupt handlers, this interrupt flag bit usually gets cleared automatically in the course of processing the interrupt, sometimes by just calling the handler at all, sometimes (eg for the U[S]ART) by reading a particular hardware register that will normally happen anyway when processing the interrupt.

From the hardware's point of view, an interrupt is asserted as long as the respective bit is set, while global interrupts are enabled. Thus, it is essential to have the bit cleared before interrupts get re-enabled again (which usually happens when returning from an interrupt handler).

Only few subsystems require an explicit action to clear the interrupt request when using interrupt handlers. (The notable exception is the TWI interface, where clearing the interrupt indicates to proceed with the TWI bus hardware handshake, so it's never done automatically.)

However, if no normal interrupt handlers are to be used, or in order to make extra sure any pending interrupt gets cleared before re-activating global interrupts (eg an external edge-triggered one), it can be necessary to explicitly clear the respective hardware interrupt bit by software. This is usually done by writing a logical 1 into this bit position. This seems to be illogical at first, the bit position already carries a logical 1 when reading it, so why does writing a logical 1 to it clear the interrupt bit?

The solution is simple: writing a logical 1 to it requires only a single OUT instruction, and it is clear that only this single interrupt request bit will be cleared. There is no need to perform a read-modify-write cycle (like, an SBI instruction), since all bits in these control registers are interrupt bits, and writing a logical 0 to the remaining bits (as it is done by the simple OUT instruction) will not alter them, so there is no risk of any race condition that might accidentally clear another interrupt request bit. So instead of writing

TIFR |= _BV(TOV0); /* wrong! */

simply use

TIFR = _BV(TOV0);

2. As long as the interrupt is enabled, even if the pin INT7:0 is configured as output, as long as the level changes appropriately, the interrupt will be triggered. How do you understand this sentence? Answer: That is to say, you turn on the interrupts int0 and int1, and define these two pins as outputs. Then, you use software to set the output levels of these two pins. When the interrupt condition is met, the interrupt occurs. Isn't this a software interrupt?

3. After configuring the external interrupt control register, mask register, and flag register, do you still need to set the IO port as an input port? Answer: Yes, but the IO port is input by default when it is powered on, so you don't need to write this instruction. In addition, setting it as output will still generate an interrupt. It is read using PINx.