ARM vectored and non-vectored interrupts

ENTRY
 b ResetHandler ; 0x00
 b HandlerUndef ; 0x04
 b HandlerSWI ; 0x08
 b HandlerPabort ; 0x0c
 b HandlerDabort ; 0x10
 b . ; 0x14
 b HandlerIRQ ; 0x18
 b HandlerFIQ ; 0x1c

 ldr pc,=HandlerEINT0 ; 0x20
 ldr pc,=HandlerEINT1
 ldr pc,=HandlerEINT2
 ldr pc,=HandlerEINT3
 ldr pc,=HandlerEINT4567
 ldr pc,=HandlerTICK ; 0x34
 b .
 b .
 ldr pc,=HandlerZDMA0 ; 0x40
 ldr pc,=HandlerZDMA1
 ldr pc,=HandlerBDMA0
 ldr pc,=HandlerBDMA1
 ldr pc,=HandlerWDT
 ldr pc,=HandlerUERR01; 0x54
 b .
 b .
 ldr pc,=HandlerTIMER0 ; 0x60
 ldr pc,=HandlerTIMER1
 ldr pc,=HandlerTIMER2 ldr
 pc,=HandlerTIMER3
 ldr pc,=HandlerTIMER4 ldr pc , = HandlerTIMER5
 ; 0x74
 b
 . ,=HandlerUTXD1; 0x94 b . b . ldr pc,=HandlerRTC ; 0xa0 b . b . b . b . b . b . ldr pc,=HandlerADC ; 0xb4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 According to DATASEET of 44b0, the instruction placed at 0x18 is b HandlerIRQ; when the program jumps to this address to execute, the code fetched by the chip at this address has been replaced by the branch instructions in the subsequent program. For example, if the chip EINT3 interrupts, the chip will jump to 0x18 to execute, and fetch instructions at 0x18 first. At this time, the instruction fetched is no longer b HandlerIRQ. b HandlerIRQ has been automatically replaced by ldr pc,=HandlerEINT3 by the chip, and then the chip executes this instruction again.

The code for non-vector interrupts is as follows:

ENTRY
 b ResetHandler ; for debug
 b HandlerUndef ; handlerUndef
 b HandlerSWI ; SWI interrupt handler
 b HandlerPabort ; handlerPAbort
 b HandlerDabort ; handlerDAbort
 b . ; handlerReserved
 b IsrIRQ
 b HandlerFIQ
 . . . . . .

IsrIRQ
 sub sp,sp,#4 ; reserved for PC
 stmfd sp!,{r8-r9}
 ldr r9,=I_ISPR
 ldr r9,[r9]
 mov r8,#0x0
0  movs r9,r9,lsr #1
 bcs %F1
 add r8,r8,#4
 b %B0
1  ldr r9,=HandleADC
 add r9,r9,r8
 ldr r9,[r9]
 str r9,[sp,#8]
 ldmfd sp!,{r8-r9,pc}
 . . . . . .

HandleADC # 4
HandleRTC # 4
HandleUTXD1 # 4
HandleUTXD0 # 4
. . . . . .

HandleEINT3 # 4
HandleEINT2 # 4
HandleEINT1 # 4
HandleEINT0 # 4; 0xc1(c7)fff84

 When an interrupt occurs, the chip automatically jumps to 0x18 for execution. The instruction at 0x18 is b IsrIRQ. The function of the IsrIRQ program is to check each bit of I_ISPR to determine what kind of interrupt has occurred, and then jump to the corresponding interrupt service program for execution according to the type of interrupt. The address definitions of various interrupt service programs are as follows:

HandleADC # 4
HandleRTC # 4
HandleUTXD1 # 4
HandleUTXD0 # 4
. . . . . .

HandleEINT3 #4

 It is worth mentioning that in the 44binit code, the vector interrupt jumps to HandlerEINT0 and the non-vector interrupt jumps to HandleEINT0. The program uses a macro to equate these two labels. Regardless of whether a vector interrupt or a non-vector interrupt is used, whether it jumps to HandleEINT0 or HandlerEINT0, the effect is the same, that is, it jumps to the address of the interrupt service program for execution.

 By the way, let me talk about the interrupt method of Philips' LPC series ARM chips. When the LPC chip receives an interrupt signal, when the interrupt is initialized, the program puts the entry address of the interrupt service program into the interrupt vector address register. Each interrupt source has an interrupt vector address register corresponding to it. There is also a register called VICVectAddr (0xffff0030). When an interrupt occurs, the hardware automatically determines which interrupt to execute, and then puts the address in the interrupt vector address register corresponding to the interrupt source into the register VICVectAddr. The code in the program interrupt vector table is executed by jumping to the address in VICVectAddr. Once an interrupt occurs, it automatically jumps to the address in VICVectAddr to execute, because at this time VICVectAddr has been replaced with the interrupt service program address of the interrupt source.

The above
 HandleADC # 4
allocates 4 bytes of storage space in the data area, which is equivalent to
 HandleADC FEILD 4.
The four bytes of storage space store the address of the interrupt service program. In the main program written in C language, how to put the entry address of the interrupt service program into this storage space? Careful readers can find that the starting address of this data area is _ISR_STARTADDRESS. In the MAIN function, just let
 (*(unsigned *)(_ISR_STARTADDRESS+0x74)) =(int)MyIsr;
MyIsr is the name of the interrupt service program, but _ISR_STARTADDRESS is an undefined value. This value is only assigned when the connector is connected. It is an undefined value in the compilation stage, so an error will be reported during compilation. #define _ISR_STARTADDRESS to an address value in SDRAM. In this case, it is 0xc7fff00.

 The initialization of interrupts includes initializing INTMSK and INTCON. If it is EINT0~7, PCONG and EXTINT need to be initialized, and
 (*(unsigned *)(_ISR_STARTADDRESS+0x74
(or other offset))) needs to be assigned a value. At the end of the interrupt service routine, I_ISPC needs to be written to clear INTPND.
If it is EINT0~7, the EXTINTPND register needs to be written before writing I_ISPC.