1. REMAP:
When it comes to REMAP, we should first think of what MAP is. I am not good at English, so I started with a quote out of context. MAP is a map, and Memory Map is a memory map. However, the reference coordinates of this map are not longitude and latitude, but addresses, which is why it is called memory mapping. In order to adapt to the needs of different memory capacity requirements, the RAM and ROM of the ARM processor itself are not large enough, so it is often necessary to expand some memories, such as Norflash, NANDFlash, SDRAM, SRAM...How can ARM identify these different memories? It can only assign an independent address to each one, which is equivalent to having a different name for each person. The address of the on-chip memory is generally fixed at the factory, and the off-chip memory has different addresses depending on the external bus chip select to which each memory is connected.
So REMAP, as the name implies, is the remapping of memory, that is, the address of some memory has changed again. I don't understand it very much. This address is not easy to remember, and it changes all the time. Isn't it troublesome? Why didn't I have this thing when I learned 51? Later, I checked some information and understood it a little. 51 is an 8-bit machine. More importantly, the main frequency of 51 is not high. The 8-bit ROM or Flash is enough to match the main frequency of 51. There is no need to insert wait instructions, so the program runs directly in ROM or Flash without affecting the speed of the system. ARM is different. ARM is a 32-bit machine, but Flash is generally 8-bit or 16-bit. There are 32-bit ones, but they seem to be very expensive. Moreover, the product size of ARM is very high, often hundreds of MB, so the process of Flash cannot reach this speed. If the program runs in Flash, too many wait instructions will be inserted, which will affect the performance of ARM. RAM generally has a faster access speed and is easy to form 32 bits, which can match the high-speed ARM. More importantly, ARM must get instructions from address 0x0 after power-on, so ROM or Flash must be mapped to address 0x0 after power-on. At that time, I had a stupid idea that since RAM is so good, why do we need ROM or Flash? Can't we just download the program to RAM? Later, I suddenly realized that RAM is a volatile memory. Nothing will be lost after power failure, and nothing will be at 0x0 after power-on. And there is another point. The interrupt vector table of ARM, which is the place where each interrupt entry address is stored, is generally placed at 0x0, that is, in ROM or Flash. In order to speed up the interrupt response speed, 0x0 should also be mapped to RAM. Therefore, ARM generally starts from ROM or Flash to complete initialization, then copies the application to RAM, and then jumps to RAM for execution.
I just talked about why we need to REMAP, and now I will talk about how to REMAP. At the beginning, I was confused. They all said REMAP, so how can we complete REMAP? I didn’t read the manual enough. In fact, what is said above is very clear. The at91sam9260 we use is even simpler. There is a special register that can be configured, MATRIX_MRCR—Master Remap Control Register. Just write 1 to the corresponding bit of this register. I also saw on the Internet that some Samsung ARMs can implement REMAP by programming the corresponding bank register to change its starting address.
Below, I will take our at91sam9260 board as an example to explain my understanding of at91sam9260 REMAP in detail. At the beginning, there is no program in Flash, and of course no REMAP. At this time, connect BMS to high, and then power on. At this time, the address 0X0 is located in the ROM inside the chip. Since the boot program seems to be solidified in the ROM, the serial port will output the words "Rom Boot...>". The starting address of the internal SRAM0 is still at 0x20 0000, and the starting address of the external Norflash is 0x1000 0000. Then we use h-flasher or J-Flash to download the generated Bin file to Norflash, that is, the starting address is 0x1000 0000. Then connect BMS to low, and Norflash is mapped at address 0X0, that is, the starting address of Norflash is 0X0. (You may ask where is the address of ROM now? I don’t know, because the address range of Norflash is 0X0~0X1F FFFF, and the starting address of ROM is 0X10 0000 by default, which is exactly within the range of Norflash, so where is the ROM at this time?) At this time, power on, because there are eight legal interrupt vectors at address 0X0, that is, the starting address of Norflash, the program will start from Norflash, then execute the startup code, initialize SMC and PMC, and then copy the interrupt vector table to the internal SRAM0, and then set the corresponding position of the MATRIX_MRCR register to 1 to implement REMAP. At this time, the starting address of Norflash changes back to 0X1000. 0000, and the starting address of the internal SRAM0 changes back to 0x0. If an exception occurs in the system, the interrupt vector will be taken from the address 0X0, that is, the internal SRAM0. The access speed of the internal SRAM is obviously higher than that of the external Norflash, so the program performance is improved. This is my understanding of at91sam9260 REMAP. Welcome to discuss and advise.
2、Bootloader:
To be honest, I still don't quite understand this concept. Maybe for a naked system, the concept of Bootloader itself is rather vague. As the name implies, Boot, boots, Load, it is more comfortable to walk with boots on (this metaphor seems to be a bad one). For ARM, it is initialized well and the vector table and data are copied to RAM, so that it can run smoothly. This is the legendary boot loader. So my understanding of Bootloader is to complete the initialization of ARM, establish the interrupt vector table and map it to RAM, copy the data segment and necessary code segment to RAM, complete REMAP, and jump to Main, this series of processes. To put it bluntly, it is the work of the startup code. I feel that this understanding is far-fetched, so please give me more advice.
3. Flashloader:
This concept is even more vague. It feels similar to Bootloader, except that Flashloader can read, write, and erase Flash, and can work with debugging software to download programs to Flash. There is an option in IAR: Use Flashloader, but it seems to be generally for on-chip Flash. Our board is an external Norflash, so it doesn't seem to be used.
Next, I will talk about my understanding of the startup code based on KEIL MDK.
Previous article:ARM rookie's growth story - Part 3
Next article:ARM assembly ADR, LDR and other pseudo instructions
Recommended ReadingLatest update time:2024-11-16 13:32
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
- Innolux's intelligent steer-by-wire solution makes cars smarter and safer
- 8051 MCU - Parity Check
- How to efficiently balance the sensitivity of tactile sensing interfaces
- What should I do if the servo motor shakes? What causes the servo motor to shake quickly?
- 【Brushless Motor】Analysis of three-phase BLDC motor and sharing of two popular development boards
- Midea Industrial Technology's subsidiaries Clou Electronics and Hekang New Energy jointly appeared at the Munich Battery Energy Storage Exhibition and Solar Energy Exhibition
- Guoxin Sichen | Application of ferroelectric memory PB85RS2MC in power battery management, with a capacity of 2M
- Analysis of common faults of frequency converter
- In a head-on competition with Qualcomm, what kind of cockpit products has Intel come up with?
- Dalian Rongke's all-vanadium liquid flow battery energy storage equipment industrialization project has entered the sprint stage before production
- Allegro MicroSystems Introduces Advanced Magnetic and Inductive Position Sensing Solutions at Electronica 2024
- Car key in the left hand, liveness detection radar in the right hand, UWB is imperative for cars!
- After a decade of rapid development, domestic CIS has entered the market
- Aegis Dagger Battery + Thor EM-i Super Hybrid, Geely New Energy has thrown out two "king bombs"
- A brief discussion on functional safety - fault, error, and failure
- In the smart car 2.0 cycle, these core industry chains are facing major opportunities!
- The United States and Japan are developing new batteries. CATL faces challenges? How should China's new energy battery industry respond?
- Murata launches high-precision 6-axis inertial sensor for automobiles
- Ford patents pre-charge alarm to help save costs and respond to emergencies
- New real-time microcontroller system from Texas Instruments enables smarter processing in automotive and industrial applications
- MSP430 communication resources IIC communication
- [TI recommended course] #Live replay: TI's new generation C2000? microcontroller#
- IAR burning program shows error
- Application of state machine principle in control program design.pdf
- The board has been mailed, please check the courier number in the post~
- Crazy Shell AI open source drone timer (LED flight status light, indicator light flashing)
- How to debug a custom Flash loader in IAR development environment?
- I can't find any information about these two chips.
- [Project source code] Determine the correspondence between the dedicated clock input pin of the FPGA and the PLL
- MCU + I2C communication response signal is abnormal