Five interrupt sources of 8051 microcontroller

When several interrupt sources request an interrupt to the CPU at the same time, they are queued according to the severity of the real-time events that occur, and the interrupt requests for the most urgent events are processed first. Therefore, the microcontroller determines the priority level of each interrupt source.

When the CPU is processing an interrupt request and another interrupt request with a higher priority occurs, the CPU temporarily suspends processing the previous interrupt and turns to processing the interrupt request with a higher priority. After the processing is completed, it continues to execute the original interrupt handler. This process is called interrupt nesting, and such an interrupt system is called a multi-level interrupt system.

Since the interruption of the CPU program by external asynchronous events is random, when the CPU turns to execute the interrupt service program, in addition to the hardware automatically pushing the power-off address, that is, the value of the 16-bit PC program counter into the stack, the user must also pay attention to protecting the relevant working registers, accumulators, flags and other information. This process is usually called protecting the scene. After completing the interrupt service program, the original working registers, accumulators, flags and other contents can be restored. This process is called restoring the scene; finally, the interrupt return instruction is executed, the power-off to PC is automatically popped up, and the main program is returned to continue executing the interrupted program.

Let's take a look at the 8051 interrupt system structure and interrupt control:

The 8051 microcontroller has five interrupt request sources and four interrupt control registers IE.IP.TCON and SCON, which are used to control the interrupt type, interrupt enable, interrupt start and stop, and the priority level of various interrupt sources.

The five interrupt sources have two priorities, and each interrupt source can be programmed as a high priority or low priority interrupt, which can achieve two-level interrupt service routine nesting. The interrupt sources of 8051 include:

INT0, INT1 pin input external interrupt source

There are three internal interrupt sources, namely the overflow interrupt source of timer T0, the overflow interrupt source of timer T1 and the send/receive interrupt source of the serial port. We will talk about the internal interrupt sources later, today we will learn about the external interrupt sources first.

　

The two external interrupt sources input from the INT0 and INT1 pins and their trigger mode control bits are latched in the lower four bits of the special function register TCON, and the format is as follows:

 

　

IE1, namely TCON.3:

External interrupt INT1 request flag. When the CPU detects an external interrupt signal on the INT1 pin, the hardware sets IE1=1 to request an interrupt. After the CPU executes the interrupt service routine, the IE1 bit is automatically cleared to 0 by the hardware.

IT1, namely TCON.2:

External interrupt INT1 request type, trigger mode control bit, set to 1 or cleared to 0 by software to control the trigger type of external interrupt 1.

   IT1=0, external interrupt 1 is set to level trigger mode. When the pin INT1 inputs a low level, IE1 is set to request an interrupt. The CPU samples the input level of INT1 during S5P2 of each machine cycle. When a low level is sampled, IE1=1 is set. When the level trigger mode is used, the external interrupt source input to the pin INT1 must maintain a valid level until the program is responded to by the CPU. At the same time, before the interrupt service program is executed, the valid level of the external interrupt source must be revoked, otherwise another interrupt will be generated.

   IT1=1, external interrupt 1 is set to edge trigger mode, and the CPU samples the level of pin INT1 in each machine cycle. If in two consecutive samplings, the pin INT1 is sampled as high level in one cycle, and then the pin INT1 is sampled as low level in the next cycle, INE1 is automatically cleared to 0 by hardware. Because the external interrupt input level is sampled once in each machine cycle, the high and low level time of the external interrupt source input must be maintained for more than 12 oscillation cycles to ensure that the CPU detects the negative jump signal, that is, the falling edge.

　

IEO, namely TCON.1: external interrupt request flag. When IE0=1, external interrupt 0 requests an interrupt from the CPU. When the CPU responds to the external interrupt, IE0 is cleared by hardware.

ITO, i.e. TCON.0: External interrupt 0 trigger mode control bit. When IT0=0, external interrupt 0 is set to edge trigger mode. When IT0=1, external interrupt 0 is set to edge level trigger mode. Its function is similar to IT1.

　

Interrupt control: In addition to some bits in the special function registers TCON and SCON that are related to interrupts, there are two special function registers IE and IP specifically used for interrupt control.

Interrupts allowed IE:

 

In the 8051 microcontroller, the special function register IE is the interrupt enable register, which controls whether the CPU allows or prohibits interrupt sources in general and whether each interrupt source allows interrupts. Its format is:

EA: Interrupt enable bit. EA=1, CPU allows interrupts; EA=0, CPU prohibits all interrupt requests.

ES: Serial interrupt enable bit. ES=1, serial port interrupt is enabled; ES=0, serial port interrupt is disabled.

EX1: T0 overflow interrupt enable bit. ET0=1, enable T0 interrupt; ET0=0, disable T0 interrupt.

EX0: External interrupt enable bit. EX0=1, enable external interrupt 0; EX0=0, disable external interrupt 0.

After the 8051 system is reset, all bits in IE are cleared to 0, which means all interrupts are disabled.

　

Interrupt priority setting register IP. The 8051 microcontroller has two interrupt priority levels. Each interrupt source can be programmed as a high priority interrupt or a low priority interrupt, and can implement two-level interrupt nesting. A high priority interrupt source can interrupt the low priority interrupt service routine being executed;

Interrupt sources of the same or lower priority cannot interrupt the interrupt program being executed. For this reason, in the 8051 interrupt system, there are two priority status triggers inside, which indicate whether the CPU is executing a high-priority or low-priority interrupt service program, thereby respectively shielding all interrupt requests and other interrupt source requests of the same level.

The special function register IP is the interrupt priority register.

 

The control bit of each interrupt source priority can be set by the user through software. The format is as follows

　

PS: Serial interrupt priority control bit. PS=1 sets the serial port to high priority interrupt; PS=0 sets it to low priority.

PT1: T1 interrupt priority control bit. PT1=1, set timer T1 as high priority interrupt; PT=0, set it as low priority.

TX1: External interrupt 1 interrupt priority control bit. PX1=1 sets external interrupt 1 as a high priority interrupt; PC1=0 sets it as a low priority.

PT1: T1 interrupt priority control bit. PT1=1, set timer T1 as high priority interrupt; PT1=0, set it as low priority.

PT0: T0 interrupt priority control bit. PT1=1, set timer T0 as high priority interrupt; PT0=0, set it as low priority.

PX0: External interrupt priority control bit. PX0=1, set INT1 to high priority. PX0=0, set to low priority.

　

After 8051 is reset, the five lower bits of IP are all cleared to 0, setting all interrupt sources to low priority interrupts.

If several interrupt sources of the same priority level request interrupts from the CPU at the same time, which one gets serviced depends on the order in which they are registered in the CPU. The CPU queries the registration number through internal hardware and decides which interrupt request to respond to first according to the natural priority. The natural priority is in the following order from high to low: external interrupt 0, timer 0, external interrupt 1, timer 1, serial interrupt.