ARM7 (lpc2146) study notes-0606-EEWORLD

Collect

1. ADS

1. Save the file name in full (including the extension)

2. If the *.tdt file is deleted, the entire project will be recompiled

3.*.axf is the debugging file of the project

4. *.scf scatter loading description file

5. The RelinFLASH version of ADS sets JTAG encryption. After downloading this version of the code, JTAG debugging cannot be used. Use the LCP ISP software provided by Zhou Ligong to erase the program in the chip and it will be OK.

2.ARM instructions

6. Little-endian mode: lower bytes are stored at lower addresses (arm7)

Big endian: lower bytes are stored at higher addresses

7. By performing the same write operation twice on a cell, the data can be written after reset. Because the SRAM controller contains a write-back buffer, the previous data is not actually written into the SRAM until the second write operation is performed.

8.VHB: 0xffe00000~0xffffffff, 16KB for each peripheral

VPB: 0xe0000000~0xe01fffff, the first peripheral 16KB

9. The basic concept of memory mapping is that each memory group has a "physical" location in the memory map.

10. BOOT Block is a piece of code that the chip design manufacturer solidifies inside the LPC2000 series ARM. It is run first after the chip is reset. Its main functions are to determine which program on the memory is running, check whether the user code is valid, determine whether the chip is encrypted, and the chip's in-application programming (IAP) and in-system programming (ISP) functions. Some of these programs can be called by users, such as the IAP code for erasing the on-chip FLASH. In order to increase the portability of user code, it is best to fix the BOOT Block code at a certain address. However, because the on-chip FLASH size of each chip is different, if the address of the BOOT Block is arranged at the end of the on-chip FLASH, then the BOOT Block address cannot be fixed. Therefore, the chip manufacturer remaps the address of the BOOT Block to the highest point of the on-chip memory space, that is, close to 2G (0x80000000), so that no matter how large the on-chip memory is, it will not affect the address of the BOOT Block. This allows user code containing IAP operations to run on different LPC2000 series ARMs without modifying the IAP operation address.

11.

— MRS Program Status Register to General Register Data Transfer Instruction

— MSR general register to program status register data transfer instruction

The format of the MSR instruction is:

MSR {condition} Program Status Register (CPSR or SPSR); field, operand

The MSR instruction is used to transfer the contents of the operand to a specific field of the program status register. The operand can be a general register or an immediate value. The field is used to set the bits in the program status register that need to be operated. The 32-bit program status register can be divided into 4 fields:

Bit [31:24] is the conditional flag bit field, represented by f;

Bit [23:16] is the status bit field, represented by s;

Bit [15:8] is the extended bit field, represented by x;

Bit [7:0] is the control bit field, represented by c;

This instruction is usually used to restore or change the contents of the program status register. When used, the domain to be operated should generally be specified in the MSR instruction.

12. The BIC instruction is used to clear certain bits of operand 1 and place the result in the destination register.

13. The SPACE directive is used to allocate a continuous storage area and initialize it to 0. The expression is the number of bytes to be allocated.

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