S5PV210 (TQ210) study notes - Nand configuration

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The Nand flash configuration of S5PV210 is similar to that of 2440 and 6410, but the difference is that S5PV210 has more powerful functions, especially the hardware ECC of S5PV210 (this article does not cover the Nand ECC configuration of S5PV210). Overall, the Nand flash configuration of S5PV210 is still very simple.

In fact, configuring a module often requires the following steps:

(1) According to the schematic diagram, clarify the wiring method of the module. For Nand flash, just check which GPIO the Nand flash is connected to, and then configure the corresponding GPIO as Nand function.

(2) Read the S5PV210 manual to understand the functions, operation methods, and register configurations of the relevant module controllers.

(3) Read the module chip manual and understand the module’s access control timing.

We follow the above steps to configure. First, the module GPIO configuration. My development board is TQ210, the Nand flash chip is K9K8G08U0B, and the wiring method is as follows:

in:

(1) The eight pins Xm0FRnB0~Xm0FRnB3, Xm0FCLE, Xm0FALE, Xm0FWEn, and Xm0FREn are connected to MP0_3. By checking the MP0_3 control register, we can see that MP0_3CON needs to be configured to 0x22222222;

(2) The four pins Xm0CSn2~Xm0CSn5 are connected to the 2~5 pins of MP0_1, so the 8~23 bits of MP0_1CON should be configured as 0x3333;

(3) The eight pins Xm0DATA0~Xm0DATA7 are connected to MP0_6, so MP0_6 should be configured as 0x22222222;

In this way, the GPIO is configured. Next, we configure the control register of Nand flash. After a general review of the register functions of Nand flash, we can find that if the ECC function is not used, only the NFCONF and NFCONT registers can be configured. Our Nand flash is an SLC type Nand with a Page size of 2048. It takes 5 cycles to write the address (these can be easily found in the Nand flash chip manual), so NFCONF should be configured as follows:

NFCONF=(3<<23)|(1<<12)|(2<<8)|(0<<4)|(1<<1); // In order: disable ECC, TACLS, TWPRH0, TWPRH1, SLC, 2K, 5 cycles.

Among them, TACLS, TWPRH0 and TWPRH1 need to be determined by reading the manual. Teacher Wei Dongshan explained the determination method. However, when I configured it completely according to the minimum time setting in the manual, I was not able to access it normally. I tried it myself. First, I set all three parameters to 7, then slowly reduced them, and finally tested them to be set to 1, 2, and 0. However, this is not necessarily the most stable. Generally speaking, a slightly larger value will be more stable, but in order not to affect the access efficiency, this value cannot be set too large. Set it according to the minimum situation first, and then appropriately increase the parameter value when a read error or other unstable phenomenon is found.

Then there is the NFCONT register. The configuration of NFCONT is even simpler. We do not set ECC, but only need to set bits 0 and 1:

NFCONT = (1<<1)|(1<<0); //Disable chip select and enable Nand

In this way, the initialization function of Nand flash comes out:

  1. void nand_init(){  
  2.     NFCONF = (3<<23)|(1<<12)|(2<<8)|(0<<4)|(1<<1);  
  3.     NFCONT = (1<<0)|(1<<1);  
  4.   
  5.     MP0_1CON &= ~(0xffff<<8);  
  6.     MP0_1CON |= 0x3333<<8;  
  7.     MP0_3CON = 0x22222222;  
  8.     MP0_6CON = 0x22222222;  
  9.   
  10.     nand_reset();  
  11. }  
As for nand_reset, usually a reset is performed after the Nand flash configuration is completed, so that the Nand flash is restored to its original state.

 

In this way, Nand flash is initialized. However, to access Nand flash, it is necessary to operate it according to the timing. When Nand mode is started, only the read operation of Nand flash needs to be implemented. For this reason, only a few read-related operations are listed here:

(1) Nand flash reset

  1. static void nand_reset(){  
  2.     nand_select_chip();  
  3.     nand_cmd(0xff);  
  4.     nand_wait();  
  5.     nand_deselect_chip();  
  6. }  
(2) Nand flash write address
  1. static void nand_addr(unsigned long page_addr, unsigned long page_offset){  
  2.     NFADDR = (page_offset>>0) & 0xFF;  
  3.     NFADDR = (page_offset>>8) & 0x7;  
  4.     NFADDR = (page_addr) & 0xFF;  
  5.     NFADDR = (page_addr>>8) & 0xFF;  
  6.     NFADDR = (page_addr>>16) & 0x07;  
  7. }  
(3) Nand flash read ID
  1. void nand_read_id(char id[]){  
  2.     int i;  
  3.   
  4.     nand_select_chip();  
  5.     nand_cmd(0x90);  
  6.   
  7.     NFADDR = 0;  
  8.   
  9.     for (i = 0; i < 5; i++)  
  10.         id[i] = nand_read();  
  11.   
  12.     nand_deselect_chip();  
  13. }  
(4) Nand flash page read data
  1. void nand_read_page(unsigned char* buf, unsigned long page_addr){  
  2.     int i;  
  3.     nand_select_chip();  
  4.     nand_cmd(0);  
  5.     nand_addr(page_addr, 0);  
  6.     nand_cmd(0x30);  
  7.     nand_wait();  
  8.     for(i = 0; i != PAGE_SIZE; ++i){  
  9.         *buf++ = nand_read();  
  10.     }  
  11.     nand_deselect_chip();  
  12. }  

The above are several important Nand flash read-related operation functions. At this point, you can add the referenced small functions to perform Nand flash operations normally. I uploaded the code I wrote to my CSDN resources, and you can refer to it if you need it. In addition, if you need to write Nand flash write operation code, you can refer to the 6410 Nand flash configuration part in my blog and the Nand flash chip manual. The principles are the same.

Keywords:S5PV210 Reference address:S5PV210 (TQ210) study notes - Nand configuration

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