Detailed explanation of MCS-51 microcontroller special function registers

1. Timer/Counter Mode Register TMOD

TMOD is an 8-bit special function register, the corresponding address is 89H, and it is not bit addressable. A mainly completes three functions:
*Determine whether to select a timer or a counter;
*Select which working mode;
*Whether to use external interrupts to control the start and stop of the timer and counter;
B The lower 4 bits of TMOD are the field that controls T0 (T0--P3.4 Timer/Counter 0 external event pulse input terminal)

The upper 4 bits of TMOD are the field that controls T1 (T1--P3.5 Timer/Counter 1 external event pulse input terminal)
C The format and meaning of the control word

a. GATE (TMOD.7)
is divided into two cases: GATE=0, the start and stop of the timer has nothing to do with INT1, but only depends on TR0;
GATE=1, the start and stop of the timer is not only controlled by TR0, but also by the control of the INT1 pin.
The timer starts working only when both are high levels;

b. C/T (TMOD.6)

is divided into two cases: C/T=0, used as a timer;
C/T=1, used as a counter;

d. M1 (TMOD.5), M0 (TMOD.4)
use M1 and M0 to control the 4 working modes of the timer/counter:
* Mode 0: M1=0, M0=0. 13-bit timer/counter mode
* Mode 1: M1=0, M0=1. 16-bit timer/counter
* Mode 2, M1=1, M0=0. 8-bit timer/counter with 8-bit initial value automatically reloaded
* Mode 3, M1=1, M0=1. Only applicable to T0, divided into two 8-bit counters, T1 stops counting

2. Timer/counter control register TCON
TCON is an 8-bit special function register, the corresponding address is 88H, which can be addressed.
A. Format and meaning of control word
a. TF1 (TCON.7), TF0 (TCON.5) ---- T1, T0 count overflow flag bit
When the counter count overflows, this position is "1". When using the query mode, this bit is used as a status bit for the CPU to
query, but it should be noted that after the query is valid, the bit should be cleared to "0" in time by software method. When using the interrupt
mode, this bit is used as the interrupt request flag bit. It is automatically cleared to 0 by the hardware after entering the interrupt service routine.
b. TR1 (TCON.6), TR0 (TCON.4) ---- Counting operation control bit
TR1 (TR0) = 1, a necessary condition for starting the timer/counter, and is also related to the state of the GATE bit.
TR1 (TR0) = 0, stops the timer/counter.
This bit can be set to 1 or cleared to 0 by software .
C. IE1 (TCON.3), IE0 (TCON.1) ---- Interrupt request flag bit of external interrupt INT1 (P3.3), INT0 (P3.2)
When there is an external interrupt request, INT1 (INT0) = 1 (completed by hardware), after the CPU responds to the interrupt,
IE1 (IE0) is cleared to 0 by the hardware
. d. IT1 (TCON.2), IT0 (TCON.0) ---- INT1 (INT0) trigger mode control bit
can be set and reset by software. IT0(IT1)=0, INT0(INT1) is a low level trigger mode;
IT0(IT1)=1, INT0(INT1) is a negative jump trigger mode;

3. Interrupt enable register IE
In the 51 interrupt system, the enable or disable of interrupts is
controlled by the 8-bit interrupt enable register IE that can be bit-addressed in the chip

EA(IE.7): main switch, if it is equal to 0, all interrupts are not allowed;
ES(IE.4): serial port interrupt enable;
ET1: timer 1 interrupt enable;
EX1: external interrupt 1 interrupt enable;
ET0: timer 0 interrupt enable;
EX0; external interrupt 0 interrupt enable;
4. The priority of the 5 interrupt sources
The interrupt service entry address of the microcontroller is as follows, and their natural priority is arranged from high to low.
External interrupt 0: 0003H;
Timer 0: 000BH;
External interrupt 1: 0013H;
Timer 1: 001BH;
Serial port: 0023H;
Using the c51 programming language, the complete syntax of the interrupt service function of this language is as follows:
Return value function name ([parameter]) [mode] [reentry] interrupt n [using n]
interrupt corresponds to the number of the interrupt source, and [using] determines the group number of the register used. Here, a
brief explanation of the register group number is required. There are 4 register groups in the 51 system, and the specific location depends on
the settings of the two bits RS0 and RS1 of psw (program status word). When running an interrupt task, different register groups are used. In c51
, the selection of the register group depends on the specification of the variable after using, which is an integer from 0 to 3.
Here are the C51 program writing methods for different interrupt service routines:
*External interrupt INT0--------void intsvr0(void) interrupt 0 using 1
*Timer/Counter T0-----void timer0(void) interrupt 1 using 1
*External interrupt INT1--------void intsvr0(void) interrupt 2 using 1
*Timer/Counter T1-----void timer0(void) interrupt 3 using 1
TMOD: Operation mode control register
Register address 89H, not bit addressable.

Sequence	B7	B6	B5	B4	B3	B2	B1	B0
Bit Notation	GATE	C/T	M1	M0	GATE	C/T	M1	M0

GATE——Gating bit
When = 0, start or disable the timer and counter by running TR0 (or TR1)
When = 1, start or disable the timer and counter by TR0*/INT0 (or TR1*/INT1)
GATE=0 Start the timer with TR0 (TR1)
GATE=1 Start the timer with INT0 (INT1)
C/T=0 Timing/counting working mode selection bit
M1M0——Working mode selection bit

T2MOD: Working mode control register
Register address 0C9H, not bit addressable

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T2O

DCEN

T2OE: Timer 2 output enable bit, when = 1, P1.0/T2 pin outputs continuous pulse signal