Status register f3
This register contains the arithmetic status bits of the ALU, the RESET status bit, and the page preselection bits for program memory greater than 512 bytes.
Status register f3 can be used as a destination register. Some flag bits are set by corresponding writes, while other bits cannot be changed by instructions. The TO and PD bits are not writable. Therefore, the result of an instruction executing the status register will be different. For example, CLR f3 is cleared to "0" by all bits except the TO and PD bits, and the "Z" position is set to "1", so the status register content is "000UU100", where U means no change.
It is recommended to use BCF, BSF or MOVWF instructions to change the content of the status register. These instructions only change the corresponding bits and do not affect other status bits. For
other instructions that affect the status bits, please refer to the instructions of the instruction system.
The status register contains 8 data bits, of which the lower 5 bits are status flag bits, and the highest bit PA2 of the upper 3 bits is not used. PA0 and PA1 are memory page select bits, and their structure is shown in the following table.
Keywords:PIC16C5X
Reference address:PIC16C5X microcontroller status register
This register contains the arithmetic status bits of the ALU, the RESET status bit, and the page preselection bits for program memory greater than 512 bytes.
Status register f3 can be used as a destination register. Some flag bits are set by corresponding writes, while other bits cannot be changed by instructions. The TO and PD bits are not writable. Therefore, the result of an instruction executing the status register will be different. For example, CLR f3 is cleared to "0" by all bits except the TO and PD bits, and the "Z" position is set to "1", so the status register content is "000UU100", where U means no change.
It is recommended to use BCF, BSF or MOVWF instructions to change the content of the status register. These instructions only change the corresponding bits and do not affect other status bits. For
other instructions that affect the status bits, please refer to the instructions of the instruction system.
The status register contains 8 data bits, of which the lower 5 bits are status flag bits, and the highest bit PA2 of the upper 3 bits is not used. PA0 and PA1 are memory page select bits, and their structure is shown in the following table.
Table 1 Structure of the status register | |||||||
PA2 | PA1 | PA0 | TO | PD | WITH | DC | C |
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Next, we will introduce the meaning of each bit. [1].C(D0): Carry/borrow flag. When executing ADDWF and SUBWF instructions, if the highest bit generates a carry or borrow, C=“1”, and the two’s complement operation is used in subtraction. [2].DC(D1): Auxiliary carry bit. When executing ADDWF and SUBWF instructions, if the lower 4 bits generate a carry or borrow, DC=“1”. [3].Z(D2): Zero flag. When the result of the arithmetic operation is 0, Z=“1”. [4].PD(D3): Low power flag. When power-on or executing CLR WDT instruction, PD=“1”. When executing SLEEP instruction, PD=“0”. [5].TO(D4): WDT overflow flag. When power-on or executing CLR WDT, SLEEP instruction, TO=“1”, when WDT overflows, TO=“0”. [6].PA0,PA1(D5,6): Program memory page select bits. For PIC16C56 microcontroller, PA0 is the program memory page select bit. PA1 is a general read/write bit. When PA=0, page 0 is selected, i.e., 000H-1FFH. When PA0=1, page 1 is selected, and the address is 200H-3FFH. For PIC16C57/58 microcontroller, PA0 and PA1 are program memory page select bits. Their values from 00-11H select pages 0-3, i.e., addresses 000-1FFH, 200H-3FFH, 400H-5FFH, 600H-7FFH. [7].PA2 (D7): general read/write bit, not used. At reset, PA2, PA1, and PA0 are cleared to "0". When power is on or the CLR WDT instruction is executed, TO and PD are both set to "1". The changes of these two bits are shown in Table 2. At power-on reset, the status of the Z, DC, and C flags are uncertain. In other reset situations (such as WDT overflow), the states of Z, DC, and C remain unchanged. The states of TO and PD during power-on reset are shown in Table 3. |
Table 2 Impact of events on TO and PD flags | |||
event | TO | PD | illustrate |
Power-on | 1 | 1 | Does not affect the PD flag |
WDT timeout overflow | 0 | X | |
SLEEP instruction | 1 | 0 | |
CLR WDT instruction | 1 | 1 |
Table 3 Status of TO and PD flags after reset | |||
TO | PD | Reset reason | |
0 | 0 | WDT timeout overflow causes SLEEP to wake up | |
0 | 1 | WDT timeout overflow (not in SLEEP state) | |
1 | 0 | MCLR adds low level to wake up from SLEEP | |
1 | 1 | At power on | |
X | X | MCLR plus low level |
After the ADDWF instruction, the carry bit C = 1 indicates a carry occurs. After the SUBWF instruction is executed, the carry bit C = 0 indicates a borrow occurs. The execution of the ADDWF or SUBWF instruction will also affect the auxiliary carry bit DC state. DC indicates a carry and borrow from the lower half byte to the upper half byte. |
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