The internal memory of MPC5554 is accessed by the external bus

In embedded applications based on dual CPUs, data interaction is usually involved. Generally speaking, there are two data interaction solutions: one is to use communication protocols such as SPI to directly transmit data. This method is only suitable for small-scale data interaction and is powerless for batch data; the other is that the dual CPUs expand external shared memory through the external bus interface, such as dual-port RAM, and realize the writing and reading of interactive data through shared memory. At present, most dual CPUs adopt this solution. Most processors are integrated with large-scale Flash memory. If the internal memory of the processor can be directly accessed and read/written through the external bus, the shared memory can be moved from off-chip to on-chip. The on-chip integrated memory is much higher in speed and reliability than the off-chip extended memory. Some processors also have integrated Flash memory with ECC check, which further improves the reliability of stored data.

1 Bus mode of processor MPC5554

MPC5554 is a 32-bit PowerPC series processor launched by Freescak. Its core is the e20026CPU with PowerPC Book E structure. It has a rich peripheral interface, including eMIOS, eQADC, DSPI, eSCI, eDMA, eTPU, FlexCAN and other modules, which can be easily connected with peripherals. This processor is widely used in automotive electronics and aerospace, with mature and reliable architecture and extensive technical support.

The external bus module of MPC5554 is called EBI (External Bus Interface) module. Like the external bus modules of other processors, it can also be expanded such as F1ash, SSRAM and asynchronous memory. The EBI module can work in many different modes, mainly the following modes:

    ◆ Single host mode, in this mode, it only responds to the commands inside the processor and ignores all external bus requests;
    ◆ External host mode, in this mode, it can respond to the commands inside the processor and external bus requests, and allow the external host to access the internal address space;
    ◆ Module disable mode, the module stops working after being disabled;
    ◆ 16-bit data bus mode, the data bus is only 16 bits, DATA[O:15] is valid, DATA[16:31] is invalid;
    ◆ Debug mode, when the system is in this mode, the EBI module is not affected and still works normally.

Among the above modes, only in the external host mode can the external host access the internal storage address of MPC5554.

2 MPC5554's external host mode

EBI Moclule Configuration Register (EBI_MCR) register is the configuration register of the EBI module, in which the EXTM bit is the external host mode selection bit of EBI. Setting it to 1 means setting the EBI module to external host mode, and setting it to 0 means it is in single host mode. When starting the module, the MDIS bit needs to be cleared to 0.

All external pins of the EBI module need to be used in external host mode. The hardware connection between MPC5554 and the external host is shown in Figure 1.

 

2.1 Internal storage space address encoding

When EBI is configured as external host mode, the external host can access the internal storage space through the bus. MPC5554, the internal address bus is 32 bits, but the external address bus is only 24 bits. A special decoding method is required to expand the 24-bit address bus to 32 bits. The EBI module decodes the 4 bits ADDR[8:11] of the external bus as 12 bits of the internal bus ADDR[0:11]. The decoding rules are:

① When ADDR[8] of the external address bus = 0, EBI ignores external data and invalid addresses.

② When ADDR[8] of the external address bus = 1, ADDR[9:11] is used to select the block for the Flash storage address; if it matches, it enters the block, and if it does not match, it returns the bus error flag.

The specific address decoding in external host mode is listed in Table 1.

 

2.2 The external host reads and writes data on the internal memory in the external master mode

After obtaining the bus control right, the external host initializes the operation on the internal memory by pulling down the TS bit. As shown in Section 2.1, when the signal on the address line matches, the internal memory space can be accessed, and the access ends when the TA signal or TEA signal appears. The TA signal is a normal end signal, and the TEA signal indicates an error on the bus. Figure 2 shows the external host reading data flow, and Figure 3 shows the external host reading data timing.

 

Figures 4 and 5 show the process and timing of external host writing data, which is roughly similar to that of reading data. However, it should be noted that the minimum delay of external host access is 3 bus cycles, and in actual systems it needs to be determined based on the specific memory block being accessed. [page]

 

 

 

3 System Design

3.1 Hardware Design

The main chip uses the processor MPC5554, which has 2 MB of internal Flash and is accessed externally through the EBI module. The external host uses the Cyclone II series FPGA chip EP2C35F672 produced by Altera. The chip has rich I/O resources. The selected 672-pin package has a maximum available I/O of 475, which is very suitable for applications with many I/O requirements. The 33,216 LE units and 105 M4K RAM blocks of EP2C35F672 can meet applications with higher requirements. There are

many types of power supplies on the circuit board. MPC5554 requires 5 V, 3.3 V, and 1.5 V power supplies, EP2C35F672 requires 3.3 V and 1.2 V power supplies, and the external input is 5 V. Two LT1765s are used to convert 5 V to 3.3 V and 1.2 V, and 1.5 V is generated from 3.3 V using NJD2783.

According to the connection shown in Figure 1, all signal lines of MPC5554, such as EXTAL, TS, TSIZ[0:1], ADDR[8:31], DATA[O:31], RD_WR, BR, BG, BB, TA, TEA, etc., are connected to the I/O of FPGA. Among them, EXTAL needs to be connected to the PLL output port of FPGA as the external input clock, and the rest are connected to the common I/O.

In order to facilitate debugging and observation results, the 1-way SCI interface of MPC5554 is led out, converted to RS232 level through MAX3232, and then connected to the serial port on the PC, and observed using the hyperterminal program.

3.2 Software Design

The design of the software requires MPC5554 to work with FPGA. First, MPC5554 needs to be configured as external master mode. There are two main configuration registers in the EBI module of MPC5554, namely EBI module configuration register EBI_MCR and EBI bus monitoring register EBI_BMCR.

The EBI module configuration register is responsible for the basic configuration of the entire module. The MDIS bit controls whether the EBI module is enabled, the EXTM bit configures whether the EBI is in external master mode, and the DBM bit controls. EBI is a 32-bit or 16-bit data bus, and EARP[O:1] is used to set the priority of the bus request.

The EBI bus monitoring register is responsible for bus monitoring control, the BMT[O:7] bit is the timeout period for bus monitoring, and the BME bit controls the enablement of bus monitoring.

In addition, there is a bus transmission error status register EBI_TESR, the TEAF bit is the transmission error flag, and the BMTF is the bus monitoring timeout flag.

The initialization procedure of the EBI module is:

 

During the read operation, the EBI module returns the data information of the corresponding address after receiving the address information sent by the FPGA; during the write operation, the EBI module writes the data information to the corresponding address according to the address information sent by the FPGA. According to the process and timing of Figures 2 to 5, the FPGA as an external host plays the role of initiating and ending data transmission. The FPGA part uses the VHDL language, and only the process part in the structure is attached.

 
 

Conclusion

The test system based on MPC5554 and FPGA described in this article has been debugged. The internal Flash memory of MPC5554 can be read and written by the external FPGA through the EBI module. Compared with the external memory, the communication read/write speed and system reliability are greatly improved. In actual applications, other processors can also simulate bus timing like the FPGA in this article. When data transmission is not required in the application, the connection can also be configured as a normal I/O for other purposes, and the hardware configuration is flexible. References

1.

Freescale MPC5553/MPC5554 Microcontroller Reference Manual 2005
2. Altera Cyclone II Device Handbook 2007