51 MCU-IIC

IIC (Inter-Intergrated Circuit) bus is a two-wire serial bus developed by PHILIPS. It is used to connect microcontrollers and their peripheral devices. IIC only needs two wires, SDA (data line) and SCL (clock). IIC supports multiple masters. Of course, there can only be one master at any time, while SPI is one master and multiple slaves. All the controlled circuits of IIC are connected in parallel on this bus, and each module and circuit has a unique address. SPI uses CS for chip selection, and as many SPIs as there are will occupy as many ports. The IIC bus has three signals during data transmission, which are: start signal, end signal and response signal.  

Hardware structure diagram of IIC bus:  


   
IIC supports multiple masters and master-slave working modes, usually master-slave working mode. In the master-slave working mode, there is only one master device (single-chip microcomputer) in the system, and the other devices are peripheral slave devices with IIC bus. In the master-slave working mode, the master device starts the data transmission (sends a start signal), generates a clock signal, and sends a stop signal. Start signal: SCL is high, SDA changes from high to low, and data transmission starts. End signal: SCL is high, SDA changes from low to high, and data transmission ends. Response signal: After receiving 8-bit data, the IC receiving data sends a specific low-level pulse to the IC sending data, indicating that the data has been received. After the CPU sends a signal to the controlled unit, it waits for the controlled unit to send a response signal. After receiving the response signal, the CPU makes a judgment on whether to continue to transmit data based on the actual situation. If no response signal is received, it is judged that the controlled unit has a fault.    

Among these signals, the start signal is necessary, and the end signal and response signal can be omitted.  

When the IIC bus transmits data, the data on the data line must remain stable during the high-level period of the clock signal. Only when the clock signal is low, the high or low level state of the data line is allowed to change. The      


  
IIC bus protocol stipulates that after each byte of data is transmitted, there must be a response signal to determine whether the data transmission has been received by the other party. The response signal is generated by the receiving device. During the high-level period of the SCL signal, the receiving device pulls SDA to a low level, indicating that the data transmission is correct and a response is generated.  


   
IIC bus timing diagram:  



Many microcontrollers do not have IIC bus interface, such as 51 microcontroller.  

Microcontroller simulates IIC bus communication:  

Start code: void start(){
    SDA = 1;
    delay();
    SCL = 1;
    delay();
    SDA = 0;
    delay();
}

  Stop code:

  
    void stop(){
    SDA = 0;
    delay();
    SCL = 1;
    delay();
    SDA = 1;
    delay();
}