Some netizens asked about the method to solve the problem of output loss of control during power-on transient in MCU application system. Here is the answer: Question: How to solve the problem of random relay action when the system is powered on?
Answer:
You can use negative logic or even complementary logic, flip logic design, etc.
Negative logic design means that the low level is valid. Most MCUs' conventional IOs are weakly pulled up during the power-on transient process, that is, the output logic 1. If you use conventional positive thinking, you will often use positive logic design, that is, high level is valid, then there is a high possibility of loss of control during the power-on transient, which can be solved by using negative logic. During the power-on transient, the IO output rises rapidly with the establishment of power. Although its logic "seems to be 0" at the beginning, as long as the output execution component is under the same power establishment conditions, the initial "logic 0" cannot cause the output execution circuit to operate. After the output execution circuit establishes the working conditions, the IO output is already logic 1.
The negative logic method can solve the problem of transient out-of-control of the same power supply system, but the execution circuit must establish working conditions before the control system or when higher reliability is required, complementary logic or flip logic design must be used. Complementary logic design refers to a series of combinations of specific 01 alternating logic as valid values, otherwise it is judged invalid; flip logic is to use the timing 01 logic to alternately appear as a valid value according to specific rules, otherwise it is judged invalid. These two are also called "combinatorial logic method" and "sequential logic method". The advantage is high reliability, but the design of the execution circuit is relatively complex. In specific applications, it needs to be flexibly selected according to actual conditions.
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